Impact of scaling on analog performance and associated modeling needs

IEEE Transactions on Electron Devices

Volumn 53, Issue 9, 2006, Pages 2160-2167

  Murmann, Boris ^a,b   Nikaeen, Parastoo ^a,b   Connelly, D J ^b   Dutton, Robert W ^a,b  

^a IEEE   (United States)

^b STANFORD UNIVERSITY   (United States)

Author keywords

CMOS; Distortion; Future performance; Scaling; Semiconductor device modeling

Indexed keywords

45-NM TECHNOLOGY; ANALOG CIRCUIT DESIGN; COMPACT MODELS; DEVICE SCALING;

ANALOG CIRCUITS; ELECTRIC DISTORTION; GATES (TRANSISTOR); SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DOPING;

CMOS INTEGRATED CIRCUITS;

EID: 33947158623     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.880372     Document Type: Article

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