An 820μW 9b 40MS/S noise-tolerant dynamic-SAR ADC in 90nm digital CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 238-240

  Giannini, Vito ^a   Nuzzo, Pierluigi ^a   Chironi, Vincenzo ^b   Baschirotto, Andrea ^b   Van Der Plas, Geert ^a   Craninckx, Jan ^a  

^a IMEC   (Belgium)

^b UNIVERSITY OF SALENTO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; COMPARATORS (OPTICAL); THERMAL NOISE;

CHARGE SHARING; DIGITAL CMOS; EFFECTIVE RESOLUTION BANDWIDTHS; NOISE-TOLERANT; PROGRAMMABLE COMPARATORS; SAR ADC; SEARCH ALGORITHMS; TIME-INTERLEAVED;

ANALOG TO DIGITAL CONVERSION;

EID: 49549118053     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523145     Document Type: Conference Paper

References (6)

1. J. Craninckx and G. Van der Plas, "A 65fJ/Conversion-Step 0-to-50Ms/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS", ISSCC Dig. Tech. Papers, pp. 246-247, Feb. 2007.
2. F. Kuttner, "A 1.2V 10b 20MSample/s Non-Binary Successive Approximation ADC in 0.13μm CMOS", ISSCC Dig. Tech. Papers, pp. 176-177, Feb. 2002.
3. A. Shrivastava, "12-bit Non-Calibrating Noise-Immune Redundant SAR ADC for System-on-a-Chip", Proc. IEEE ISCAS, pp. 1515-1518, May 2006.
4. K.S. Tan, S. Kiriaki, M. de Wit et al, "Error Correction Techniques for High-Performance Differential A/D Converters", IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 1318-1327. Dec. 1990.
5. M. Hesener, T. Eichler, A. Hanneberg, et al. "A 14b 40MS/s Redundant SAR ADC with 480MHz Clock in 0.13pm CMOS", ISSCC Dig. Tech. Papers, pp. 248-249, Feb. 2007.
6. A.M. Abo, P.R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter", IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999.