14-Bit intrinsic accuracy Q2 Random Walk CMOS DAC

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 12, 1999, Pages 1708-1718

  Van Der Plas, Geert A M ^a   Vandenbussche, Jan ^a   Sansen, Willy ^a   Steyaert, Michel S J ^a   Gielen, Georges G E ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

DIFFERENTIAL EQUATIONS; DIGITAL TO ANALOG CONVERSION; ENERGY UTILIZATION; INTEGRAL EQUATIONS;

MIXED ANALOG-DIGITAL INTEGRATED CIRCUITS; RANDOM WALK SWITCHING METHOD;

CMOS INTEGRATED CIRCUITS;

EID: 0033280679     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.808896     Document Type: Article

References (14)

1. H. Samueli, "Broadband communications ICs: Enabling high-bandwidth connectivity in the home and office," in Proc. IEEE 1999 ISSCC, Feb. 1999, pp. 26-30.
2. J. Bastos, M. Steyaert, and W. Sansen, "A high yield 12-bit 250-MS/s CMOS D/A converter," in Proc. IEEE 1996 CICC, May 1996, pp. 431-434.
3. 2," IEEE J. Solid-State Circuits, vol. 33, pp. 1948-1958, Dec. 1998.
4. J. Bastos, A. M. Marques, M. S. J. Steyaert, and W. Sansen, "A 12-bit intrinisic accuracy high-speed CMOS DAC," IEEE J. Solid-State Circuits, vol. 33, pp. 1959-1969, Dec. 1998.
5. Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, and N. Yazawa, "A 10-b 70-MS/s CMOS D/A converter," IEEE J. Solid-State Circuits, vol. 26, pp. 637-642, Apr. 1991.
6. T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, and Y. Horiba, "An 80-MHz 8-bit CMOS D/A converter," IEEE J. Solid-State Circuits, vol. SC-21, pp. 983-988, Dec. 1986.
7. A. R. Bugeja, B.-S. Song, P. L. Rakers, and S. F. Gillig, "A 14b 100 MSample/s CMOS DAC designed for spectral performance," in Proc. IEEE 1999 ISSCC, Feb. 1999, pp. 148-149.
8. K. Lakshmikumar, R. Hadaway, and M. Copeland, "Characterization and modeling of mismatch in MOS transistors for precision analog design," IEEE J. Solid-State Circuits, vol. SC-21, pp. 1057-1066, Dec. 1986.
9. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol. 24, pp. 1433-1439, Oct. 1989.
10. B. Razavi, Principles of Data Conversion System Design. Piscataway, NJ: IEEE Press, 1995, pp. 62-63.
11. D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, "Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits," IEEE J. Solid-State Circuits, vol. 28, pp. 420-429, Apr. 1993.
12. M. Ingels and M. Steyaert, "Design strategies and decoupling techniques for reducing the effects of electrical interference in mixed-mode IC's," IEEE J. Solid-State Circuits, vol. 32, pp. 1136-1141, July 1997.
13. G. Van der Plas, J. Vandenbussche, G. Gielen, and W. Sansen, "Mondriaan: A tool for automated layout synthesis of array-type analog blocks," in Proc. IEEE 1998 CICC, May 1998, pp. 485-488.
14. H. P. Tuinhout and M. Vertregt, "Test structures for investigation of metal coverage effects on MOSFET matching," in Proc. IEEE 1997 Int. Conf. Microelectronic Test Structure, Mar. 1997, vol. 10, pp. 179-183.