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Volumn 43, Issue 12, 2008, Pages 2620-2630

An over-60 dB true rail-to-rail performance using correlated level shifting and an opamp with only 30 db loop gain

Author keywords

Correlated double sampling (CDS); Correlated level shifting (CLS); Pipelined analog to digital converter; Rail to rail

Indexed keywords

ANALOG TO DIGITAL CONVERSION; DATA STORAGE EQUIPMENT; DIGITAL TO ANALOG CONVERSION; ERRORS; FREQUENCY CONVERTERS; IMAGE SENSORS; MULTICARRIER MODULATION; NETWORKS (CIRCUITS); OPERATIONAL AMPLIFIERS;

EID: 57849122662     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2006312     Document Type: Conference Paper
Times cited : (124)

References (17)
  • 1
    • 0023346287 scopus 로고
    • Switched-capacitor circuits with reduced sensitivity to amplifier gain
    • May
    • K. Nagaraj, "Switched-capacitor circuits with reduced sensitivity to amplifier gain", IEEE Trans. Circuits Syst., vol. CAS-34, pp. 571-574, May 1987.
    • (1987) IEEE Trans. Circuits Syst , vol.CAS-34 , pp. 571-574
    • Nagaraj, K.1
  • 2
    • 0030286542 scopus 로고    scopus 로고
    • Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization
    • Nov
    • C. C. Enz and G. C. Temes, "Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization", Proc. IEEE, vol. 84, pp. 1584-1614, Nov. 1996.
    • (1996) Proc. IEEE , vol.84 , pp. 1584-1614
    • Enz, C.C.1    Temes, G.C.2
  • 3
    • 0027887139 scopus 로고
    • A high-swing 2-V CMOS operational amplifier with replica-amp gain enhancement
    • Dec
    • P. C. Yu and H.-S. Lee, "A high-swing 2-V CMOS operational amplifier with replica-amp gain enhancement", IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1265-1272, Dec. 1993.
    • (1993) IEEE J. Solid-State Circuits , vol.28 , Issue.12 , pp. 1265-1272
    • Yu, P.C.1    Lee, H.-S.2
  • 4
    • 0025568946 scopus 로고
    • A fast-settling CMOS op amp for SC circuits with 90-dB DC gain
    • Jun
    • K. Bult and G. J. G. M. Geelen, "A fast-settling CMOS op amp for SC circuits with 90-dB DC gain", IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 1379-1384, Jun. 1990.
    • (1990) IEEE J. Solid-State Circuits , vol.25 , Issue.6 , pp. 1379-1384
    • Bult, K.1    Geelen, G.J.G.M.2
  • 5
    • 10444266682 scopus 로고    scopus 로고
    • A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR
    • Dec
    • Y. Chiu, P. R. Gray, and B. Nikohc, "A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR", IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2139-2151, Dec. 2004.
    • (2004) IEEE J. Solid-State Circuits , vol.39 , Issue.12 , pp. 2139-2151
    • Chiu, Y.1    Gray, P.R.2    Nikohc, B.3
  • 6
    • 4444321512 scopus 로고    scopus 로고
    • A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique
    • Sep
    • J. Li and U.-K. Moon, "A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique", IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1468-1476, Sep. 2004.
    • (2004) IEEE J. Solid-State Circuits , vol.39 , Issue.9 , pp. 1468-1476
    • Li, J.1    Moon, U.-K.2
  • 7
    • 0032664038 scopus 로고    scopus 로고
    • A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter
    • May
    • A. M. Abo and P. R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter", IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999.
    • (1999) IEEE J. Solid-State Circuits , vol.34 , Issue.5 , pp. 599-606
    • Abo, A.M.1    Gray, P.R.2
  • 8
    • 0020906580 scopus 로고
    • An improved frequency compensation technique for CMOS operational amplifiers
    • Dec
    • B. K. Ahuja, "An improved frequency compensation technique for CMOS operational amplifiers", IEEE J. Solid-State Circuits, vol. SC-18, no. 2, pp. 629-33, Dec. 1983.
    • (1983) IEEE J. Solid-State Circuits , vol.SC-18 , Issue.2 , pp. 629-633
    • Ahuja, B.K.1
  • 9
    • 0021622790 scopus 로고
    • Design techniques for cascoded CMOS op amps with improved PSRR and common-mode input range
    • Dec
    • D. B. Ribner and M. A. Copeland, "Design techniques for cascoded CMOS op amps with improved PSRR and common-mode input range", IEEE J. Solid-State Circuits, vol. SC-19, no. 12, pp. 919-25, Dec. 1984.
    • (1984) IEEE J. Solid-State Circuits , vol.SC-19 , Issue.12 , pp. 919-925
    • Ribner, D.B.1    Copeland, M.A.2
  • 10
    • 49549084393 scopus 로고    scopus 로고
    • An over-60 dB true rail-to-rail performance using correlated level shifting and an opamp with 30 dB loop gain
    • Papers, Feb
    • B. R. Gregoire and U.-K. Moon, "An over-60 dB true rail-to-rail performance using correlated level shifting and an opamp with 30 dB loop gain", in Proc. IEEE Int. Solid-State Circuits Conf. Dig, Tech. Papers, Feb. 2008, pp. 540-541.
    • (2008) Proc. IEEE Int. Solid-State Circuits Conf. Dig, Tech , pp. 540-541
    • Gregoire, B.R.1    Moon, U.-K.2
  • 11
    • 0034995986 scopus 로고    scopus 로고
    • Correction of operational amplifier gain error in pipelined A/D converters
    • May
    • A. Ali and K. Nagaraj, "Correction of operational amplifier gain error in pipelined A/D converters", in Proc. IEEE Int. Symp. Circuits Syst., May 2001, vol. I, pp. 568-571.
    • (2001) Proc. IEEE Int. Symp. Circuits Syst , vol.1 , pp. 568-571
    • Ali, A.1    Nagaraj, K.2
  • 12
    • 0027853599 scopus 로고
    • A 15-b 1-Msample/s digitally self-calibrated pipeline ADC
    • Dec
    • A. N. Karanicolas, H.-S. Lee, and K. L. Bacrania, "A 15-b 1-Msample/s digitally self-calibrated pipeline ADC", IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1207-1215, Dec. 1993.
    • (1993) IEEE J. Solid-State Circuits , vol.28 , Issue.12 , pp. 1207-1215
    • Karanicolas, A.N.1    Lee, H.-S.2    Bacrania, K.L.3
  • 13
    • 0026999467 scopus 로고
    • Digital-domain calibration of multistep analog-to-digital converters
    • Dec
    • S. H. Lee and B. S. Song, "Digital-domain calibration of multistep analog-to-digital converters", IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1679-1688, Dec. 1992.
    • (1992) IEEE J. Solid-State Circuits , vol.27 , Issue.12 , pp. 1679-1688
    • Lee, S.H.1    Song, B.S.2
  • 14
    • 0032313025 scopus 로고    scopus 로고
    • A digital background calibration technique for time-interleaved analog-to-digital converters
    • Dec
    • D. Fu, K. C. Dyer, S. H. Lewis, and P. J. Hurst, "A digital background calibration technique for time-interleaved analog-to-digital converters", IEEE J. Solid-State Circuits, vol. 33, pp. 1904-1911, Dec. 1998.
    • (1998) IEEE J. Solid-State Circuits , vol.33 , pp. 1904-1911
    • Fu, D.1    Dyer, K.C.2    Lewis, S.H.3    Hurst, P.J.4
  • 15
    • 18744380443 scopus 로고    scopus 로고
    • A 0.9 V 12 mW 5-MSPS algorithmic ADC with 77-dB SFDR
    • Apr
    • J. Li, G.-C. Ahn, D. Y. Chang, and U.-K. Moon, "A 0.9 V 12 mW 5-MSPS algorithmic ADC with 77-dB SFDR", IEEE J. Solid State Circ., vol. 40, no. 4, pp. 960-969, Apr. 2005.
    • (2005) IEEE J. Solid State Circ , vol.40 , Issue.4 , pp. 960-969
    • Li, J.1    Ahn, G.-C.2    Chang, D.Y.3    Moon, U.-K.4
  • 16
    • 29044434354 scopus 로고    scopus 로고
    • Split ADC architecture for deterministic digital background calibration of a 16 bit 1-MS/s ADC
    • Dec
    • J. McNeill, M. C. W. Coln, and B. J. Larivee, "Split ADC architecture for deterministic digital background calibration of a 16 bit 1-MS/s ADC", IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2437-2445, Dec. 2005.
    • (2005) IEEE J. Solid-State Circuits , vol.40 , Issue.12 , pp. 2437-2445
    • McNeill, J.1    Coln, M.C.W.2    Larivee, B.J.3
  • 17
    • 0348233280 scopus 로고    scopus 로고
    • A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification
    • Dec
    • B. Murmann and B. E. Boser, "A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification", IEEE. J. Solid-State Circuits, vol. 38, pp. 2040-2050, Dec. 2003.
    • (2003) IEEE. J. Solid-State Circuits , vol.38 , pp. 2040-2050
    • Murmann, B.1    Boser, B.E.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.