A 350MHz low-OSR ΔE current-steering DAC with active termination in 0.13μm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Clara, Martin ^a   Klatzer, Wolfgang ^a   Wiesbauer, Andreas ^a   Straeussnigg, Dietmar ^a  

^a INFINEON TECHNOLOGIES AUSTRIA AG   (Austria)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144461783     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. R. T Baird, T. S. Fiez, "Linearity Enhancement of Multi-bit AI A/D and D/A Converters using Data Weighted Averaging," IEEE T. on Circuits and Systems II, pp. 753-762, Dec., 1995.
2. M. Clara et al., "Nonlinear Distortion in Current-Steering D/A-Converters due to Asymmetrical Switching Errors," IEEE ISCAS Proceedings, vol. 1, pp. 285-288, May, 2004.
3. R. Adams et al., "A 113-dB SNR Oversampling DAC with Segmented Noise-Shaped Scrambling," IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1871-1998, Dec., 1998.