A 12-b, 60-MSample/s cascaded folding and interpolating ADC

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 12, 1997, Pages 1876-1886

  Vorenkamp, Pieter ^a,b,c,d,e,f   Roovers, Raf ^a,c,d,g  

^a IEEE   (United States)

^b NXP SEMICONDUCTORS   (Netherlands)

^c BROADCOM CORPORATION   (United States)

^d PHILIPS RESEARCH LABORATORIES   (Netherlands)

^e UNIVERSITY OF TWENTE   (Netherlands)

^f Analog Integrated Electronics Group   (France)

^g UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

Analog to digital conversion; BiCMOS integrated circuit; Folding; Interpolating

Indexed keywords

AMPLIFIERS (ELECTRONIC); BANDWIDTH; BIPOLAR INTEGRATED CIRCUITS; CASCADE CONNECTIONS; CMOS INTEGRATED CIRCUITS; DIGITAL COMMUNICATION SYSTEMS; INTERPOLATION; OPTIMIZATION; SIGNAL DISTORTION; SIGNAL TO NOISE RATIO;

INTEGRATED TRACK AND HOLD AMPLIFIERS; TOTAL HARMONIC DISTORTION (THD);

ANALOG TO DIGITAL CONVERSION;

EID: 0031378861     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.643646     Document Type: Article

References (11)

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9. 2," in ISSCC'97 Dig. Tech. Papers, Feb. 1997, pp. 136-137.
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