Integration and innovation in the nanoelectronics era

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages 36-41

  Chou, Sunlin ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144439482     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (32)

1. Gordon Moore, "Cramming more components onto integrated circuits," Electronics, vol. 38, no. 8, pp. 114-117, April 19, 1965.
2. Gordon Moore, "No Exponential is Forever: But 'Forever' Can Be Delayed!," ISSCC Dig. Tech. Papers, pp. 20-23, Feb., 2003.
3. Alan Niebel, "Flash Memory Applications and Markets: 2004-2009," Web-Feet Research Inc., Sept., 2004.
4. Alex Slawsby, "Worldwide WLAN-Enabled Mobile Device 2004-2008 Forecast and Analysis," IDC Doc. #32095, Oct., 2004.
5. Intel Research and Development, "Architecting the Era of Tera," Feb., 2004.
6. Pat Gelsinger, "Microprocessors for the New Millenium: Challenges, Opportunities, and New Frontiers," ISSCC Dig. Tech. Papers, pp. 22-25, Feb., 2001.
7. S. Naffziger, T. Grutkowski, B. Stackhouse, "The Implementation of a 2-Core Multi-Threaded Itanium®-Family Processor," ISSCC Dig. Tech. Papers, Paper 10.1, pp. 182-183, Feb., 2005.
8. C. Calwell, C. Hershberg, and D. Hiller, "Forging Ahead with Desktop PC Power Supply Efficiency Improvements," Intel Technology Symposium, Sept. 8, 2004.
9. R. Tessier and W. Burleson, "Reconfigurable Computing for Digital Signal Processing: A Survey," J. VLSI Signal Processing 28, pp. 7-27, 2001.
10. G. Chinn, S. Desai, E. DiStafano, K. Ravichandran, and S. Thakkar, "Mobile PC Platforms Enabled with Intel® Centrino™ Mobile Technology," Intel Technology Journal, pp. 6-15, May, 2003.
11. R. Morrow "Wireless Network Coexistence," McGraw Hill, July, 2004.
12. M. Bohr, "Nanotechnology Goals and Challenges for Electronic Applications," IEEE Transactions on Nanotechnology, vol. 1, no. 1, p. 56, March, 2002.
13. K. Mistry, M. Armstrong, C. Auth, et al., "Delaying Forever: Uniaxial Strained Silicon Transistors in a 90nm CMOS Technology," Symp. VLSI Tech., pp.50-51, June, 2004.
14. th International Conference on Microelectronics and Interfaces, pp. 1-3, March, 2004.
15. B. Doyle, B. Boyanov, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios, R. Chau, "Tri-Gate Fully-Depleted CMOS Transistors: Fabrication, Design and Layout," Symp. VLSI Technology, pp. 133-134, June, 2003.
16. B. Chandran, R. Mahajan, M. Bohr, C. Jan, Q. Vu, "The Mechanical Side of Ultra-Low k: Can it Take the Strain?," Future Fab Intl., vol. 17, pp. 121-124, June 21, 2004.
17. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu and J. Yamada, "1-V Power Supply High-Speed Digital Circuit Technology with Multi-threshold-Voltage CMOS," IEEE J. Solid-State Circuits, vol. 8, no. 30, pp. 847-854, 1995.
18. S. Borkar, "Circuit Techniques for Subthreshold Leakage Avoidance, Control, and Tolerance," IEDM Tech. Dig., pp. 421-424, Dec., 2004.
19. S. Narendra, S. Borkar, V. De, D. Antoniadis, A. Chandrakasan, "Scaling of Stack Effect and its Application for Leakage Reduction," International Symposium on Low Power Electronics and Devices, pp. 195-200, Aug. 6-7, 2001.
20. K. Zhang, U. Bhattacharya, Z. Chen, et al., "An SRAM Design on 65nm CMOS Technology with Integrated Leakage Reduction Scheme," Symp. VLSI Circuits, pp. 294-295, June, 2004.
21. K. Zhang, U. Bhattacharya, Z. Chen, et al., "A 3-GHz 70Mb SRAM in 65nm CMOS Technology with Integrated Column-Based Dynamic Power Supply," ISSCC Dig. Tech. Papers, Paper 26.1, pp. 474-475, Feb., 2005.
22. A. Chandrakasan, S. Sheng, and R. W. Brodersen, "Low-power CMOS digital design," IEEE J. Solid-State Circuits, vol. 27, pp. 473-484, April 1992.
23. K. Kuhn, R. Basco, D. Becher, M. Hattendorf, P. Packan, I. Post, P. Vandervoorn, I. Young, "A Comparison of State-of-the-Art NMOS and SiGe HBT Devices for Analog/Mixed-signal/RF Circuit Applications," Symp. VLSI Circuits, pp. 224-225, June, 2004.
24. B. Boser, B. Wooley, "The Design of Sigma-Delta Modulation Analog-to-Digital Converters," IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1298-1308, December 1988.
25. S. Chou and P. Gelsinger, "Building the Digital Future," Intel Developer Forum, Sept., 2002.
26. K Kukli, "Atomic Layer Deposition Chemistry, Mechanisms and Related Physical Properties of High Permittivity Dielectric Oxides," Extended Abstracts of International Workshop on Gate Insulator (IEEE Cat. No.03EX765). Piscataway, NJ, USA: IEEE, pp. 106-111, 2003.
27. M. Hazani, D. Shvarts, D. Peled, V. Sidorov, and R. Naaman, "Self-Assembled Carbon-Nanotube-Based Field-Effect Transistors," Applied Physics Letters, vol. 85, no. 21, pp. 5025 - 5027, 2004.
28. A. M. Morales and C. M. Lieber, "A Laser Ablation Method for the Synthesis of Crystalline Semiconductor Nanowires," Science, 279(5348): pp. 208-211, 1998.
29. T. Ashley, A.R. Barnes, L. Buckle, et al, "Novel InSb-Based Quantum Well Transistors for Ultra-High Speed, Low Power Logic Applications," 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, Beijing, China, pp. 2253-2256, Oct. 18-21, 2004.
30. S. Wolf, D. Awschalom, R. Buhrman, et al., "Spintronics: A Spin-Based Electronics Vision for the Future," Science vol. 294, pp. 1489-1495, Nov., 2001.
31. rd International Extreme Ultraviolet Lithography Symposium, Miyazaki, Japan, Nov. 1-4, 2004.
32. M. Crowley, A. Al-Shamma, D. Bosch, et al, "512Mb PROM with 8 layers of Antifuse/Diode Cells," ISSCC Dig. Tech. Papers, pp. 284-285, Feb., 2003.