A 1-GS/s 11-bit ADC with 55-dB SNDR, 250-mW power realized by a high bandwidth scalable time-interleaved architecture

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 12, 2006, Pages 2650-2657

  Gupta, Sandeep K ^a,b   Inerfield, Michael A ^a,b   Wang, Jingbo ^a,b  

^a IEEE   (United States)

^b Teranetics Inc   (United States)

Author keywords

Analog to digital conversion; Double sampling; ENOB; Figure of merit (FOM); High accuracy ADC; High speed ADC; Offset and gain error; Phase skew correction; Pipeline ADC; Sampling networks; Switched capacitor circuits; Time interleaving; Timing

Indexed keywords

CORE POWER; NYQUIST RATE; PIPELINED ARCHITECTURE; SAMPLING SWITCH;

BANDWIDTH; BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; DATA TRANSFER; NETWORKS (CIRCUITS); PIPELINE PROCESSING SYSTEMS; SIGNAL TO NOISE RATIO;

ANALOG TO DIGITAL CONVERSION;

EID: 33845604986     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.884331     Document Type: Conference Paper

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