A 65fJ/conversion-step 0-to-50MS/s 0-to-0.7mW 9b charge-sharing SAR ADC in 90nm digital CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 246-248

  Craninckx, Jan ^a   Van Der Plas, Geert ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CHARGE; ELECTRIC POWER UTILIZATION; NATURAL FREQUENCIES;

ASYNCHRONOUS CONTROLLERS; STATIC POWER;

CMOS INTEGRATED CIRCUITS;

EID: 34548850306     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373386     Document Type: Conference Paper

References (4)

1. J. McCreary and P. Gray, "All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques - Part I," IEEE J. Solid-State Circuits, vol. 10, no. 6, pp. 371-379, Dec., 1975.
2. N. Verma and A. Chandrakasan, "A 25μW 100kS/s 12b ADC for Wireless Micro-Sensor Applications", ISSCC Dig. Tech. Papers, pp. 222-223, Feb., 2006
3. S. Chen and R. Brodersen, "A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13μm CMOS," ISSCC Dig. Tech. Papers, pp. 574-575, Feb., 2006
4. G. Van der Plas, S. Decoutere and S. Donnay, "A0.16pF/conversion- Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process", ISSCC Dig. Tech. Papers, pp. 566-567, Feb., 2006.