A 130 nm CMOS 6-bit full nyquist 3 GS/s DAC

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 11, 2008, Pages 2396-2403

  Wu, Xu ^a   Palmers, Pieter ^a   Steyaert, Michiel S J ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

CMOS; Current steering; Digital to analog converter; Full nyquist; High speed; Pseudo segmentation

Indexed keywords

CMOS; CURRENT-STEERING; DIGITAL-TO-ANALOG CONVERTER; FULL NYQUIST; HIGH SPEED; PSEUDO-SEGMENTATION;

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; DIGITAL ARITHMETIC; DIGITAL INTEGRATED CIRCUITS; HYBRID COMPUTERS;

DIGITAL TO ANALOG CONVERSION;

EID: 57049151915     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2004527     Document Type: Article

References (17)

1. J. Bastos, A. M. Marques, M. S. J. Steyaert, and W. Sansen, "A 12-bit intrinsic accuracy high-speed CMOS DAC," IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1959-1969, Dec. 1998.
2. A. V. d. Bosch, M. A. F. Borremans, M. S. J. Steyaert, and W. Sansen, "A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter," IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 315-324, Mar. 2001.
3. C.-H. Lin and K. Bult, "A 10-b 500-MSamples/s CMOS DAC in 0.6 mm," IEEE J. Solid-State. Circuits, vol. 33, no. 12, pp. 1948-1958, Dec. 1998.
4. J. Deveugele and M. S. J. Steyaert, "A 10 b 250 MS/s binary-weighted current-steering DAC," IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 320-329, Feb. 2006.
5. S. Luschas and H.-S. Lee, "Output impedance requirements for DACs," in Proc. Int. Symp. Circuits and Systems (ISCAS '03), May 2003, vol. 1, pp. I-861-I-864.
6. T. Chen and G. Gielen, "The analysis and improvement of a currentsteering DACs dynamic SFDR, Part I: The cell-dependent delay differences," IEEE Trans. Circuits, vol. 53, pp. 3-15, Jan. 2006.
7. K. Doris, J. Briaire, D. Leenaerts, M. Vertregt, and A. V. Roermund, "A 12 b 500 MS/s DAC with >70 dB SFDR up to 120MHzin0.18-μm CMOS," in IEEE ISSCC Dig. Tech. Papers, Feb. 2005, pp. 116-117.
8. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol. 24, no. 10, pp. 1433-1439, Oct. 1989.
9. G. V. d. Plas, J. Vandenbussche, A. V. d. Bosch, M. S. J. Steyaert, W. Sansen, and G. Gielen, "MOS transistor mismatch for high, accuracy applications," in Proc. IEEE Benelux Workshop on Circuits, Systems and Signal Processing (ProRISC), Nov. 1999, pp. 529-533.
10. Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, and N. Yazawa, "A 10-b 70-MS/s CMOS D/A converter," IEEE J. Solid-State Circuits, vol. 26, no. 4, pp. 637-642, Apr. 1991.
11. A. Boni, A. Pierazzi, and D. Vecchi, "LVDS I/O interface for Gb/s-perpin operation in 0.35-μm CMOS," IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 706-711, Apr. 2001.
12. A. Van den Bosch, M. S. J. Steyaert, and W. Sansen, "Solving static and dynamic performance limitations for high speed D/A converters," in Proc. 10th Workshop on Advances in Analog Circuit Design, Apr. 2001.
13. P. Schvan, D. Pollex, and T. Bellingrath, "A 22 GS/s 6 b DAC with integrated digital ramp generator," in IEEE ISSCC Dig. Tech. Papers, Feb. 2005, pp. 122-588.
14. D. Baranauskas and D. Zelenin, "A 0.36 W 6 b up to 20 GS/s DAC for UWB wave formation," in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 2380-2389.
15. J. J. Jung, B. Park, S. S. Choi, S. I. Lim, and S. Kim, "A 6-bit 2.704 Gsps DAC for DS-CDMA UWB," in IEEE Asia Pacific Conf. Circuits and Systems (APCCAS '06), Dec. 2006, pp. 347-350.
16. B. Schafferer and R. Adams, "A 3 V CMOS 400 mW 14 b 1.4 GS/s DAC for multi-carrier applications," in IEEE ISSCC Dig. Tech. Papers, Feb. 2004, pp. 360-361.
17. A. V. d. Bosch, M. S. J. Steyaert, and W. Sansen, "SFDR-bandwidth limitations for high speed high resolution current steering CMOS D/A converters," in Proc. 6th IEEE Int. Conf. Electronics, Circuits and Systems (ICECS '99), Sep. 1999, vol. 3, pp. 1193-1196.