ADC-based serial I/O receivers

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 57, Issue 9, 2010, Pages 2248-2258

  Chen, E H ^a   Yang, Chih Kong Ken ^a  

^a Engineering IV   (United States)

Author keywords

analog to digital converter (ADC); clock and data recovery (CDR); equalization; I O link; receiver

Indexed keywords

BUDGET CONTROL; CLOCK AND DATA RECOVERY CIRCUITS (CDR CIRCUITS); CMOS INTEGRATED CIRCUITS; ECONOMIC AND SOCIAL EFFECTS; FREQUENCY CONVERTERS; INTEGRATED CIRCUIT DESIGN; MIXED SIGNAL INTEGRATED CIRCUITS; RECEIVERS (CONTAINERS);

ANALOG TO DIGITAL CONVERTERS; CLOCK AND DATA RECOVERY; CURRENT FABRICATION; DIGITAL RECEIVERS; EQUALIZATION; LOW-POWER DISSIPATION; PERFORMANCE TRADE-OFF; PROCESSING TECHNIQUE;

ANALOG TO DIGITAL CONVERSION;

EID: 77957751880     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2010.2071431     Document Type: Article

References (59)

1. V. Balan, J. Caroselli, J.-G. Chern, C. Chow, R. Dadi, C. Desai, L. Fang, D. Hsu, P. Joshi, H. Kimura, C. Y. Liu, T.-W. Pan, R. Park, C. You, Y. Zeng, E. Zhang, and F. Zhong, "A 4.8-6.4-Gb/s serial link for backplane applications using decision feedback equalization," IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1957-1967, Sep. 2005.
2. K.-L. J. Wong, A. Rylyakov, and C.-K. K. Yang, "A 5-mW 6-Gb/s quarter-rate sampling receiver with a 2-Tap DFE using soft decisions," IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 881-888, Apr. 2007.
3. Y.-S. Sohn, S.-J. Bae, H.-J. Park, C.-H. Kim, and S.-I. Cho, "A 2.2 Gbps CMOS look-ahead DFE receiver for multidrop channel with pin-to-pin time skew compensation," in Proc. IEEE Custom Integr. Circuits Conf., 2003, pp. 473-476.
4. V. Stojanovic, A. Ho, B. Garlepp, F. Chen, J. Wei, E. Alon, C. Werner, J. Zerbe, and M. A. Horowitz, "Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver," in VLSI Circuits Symp. Dig. Tech. Papers, 2004, pp. 348-351.
5. M. Harwood, N. Warke, R. Simpson, T. Leslie, A. Amerasekera, S. Batty, D. Colman, E. Carr, V. Gopinathan, S. Hubbins, P. Hunt, A. Joy, P. Khandelwal, B. Killips, T. Krause, S. Lytollis, A. Pickering, M. Saxton, D. Sebastio, G. Swanson, A. Szczepanek, T. Ward, J. Williams, R. Williams, and T. Willwerth, "A 12.5 Gb/s SerDes in 65 nm CMOS using a baud-rate ADC with digital receiver equalization and clock recovery," in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf. (ISSCC2007), pp. 436-591.
6. J. Cao, B. Zhang, U. Singh, D. Cui, A. Vasani, A. Garg, W. Zhang, N. Kocaman, D. Pi, B. Raghavan, H. Pan, I. Fujimori, and A. Momtaz, "A 500 mW digitally calibrated AFE in 65 nm CMOS for 10 Gb/s serial links over backplane and multimode fiber," in Dig. Tech. Papers IEEE Solid-State Circuits Int. Conf. (ISSCC 2009), pp. 370-371.
7. O. E. Agazzi, M. R. Hueda, D. E. Crivelli, H. S. Carrer, A. Nazemi, G. Luna, F. Ramos, R. Lopez, C. Grace, B. Kobeissy, C. Abidin, M. Kazemi, M. Kargar, C. Marquez, S. Ramprasad, F. Bollo, V. Posse, S. Wang, G. Asmanis, G. Eaton, N. Swenson, T. Lindsay, and P. Voois, "A 90 nm CMOS DSP MLSD transceiver with integrated AFE for electronic dispersion compensation of multimode optical fibers at 10 Gb/s," IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2939-2957, Dec. 2008.
8. A. Sheikholeslami, B. Payne, and J. Lin, "Will ADCs overtake binary front-ends in backplane signaling?," presented at the IEEE Int. Solid-State Circuits Conf., San Francisco, CA, 2009, Special Evening Session, SE3.
9. I. Mehr, P. C. Maulik, and D. Paterson, "A 12-bit integrated analog front end for broadband wireline networks," IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 302-309, Mar. 2002.
10. M. Moyal, M. Groepl, and T. Blon, "A 25-kft, 768-kb/s CMOS analog front end for multiple-bit-rate DSL transceiver," IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1961-1972, Dec. 1999.
11. M. Bathaee, H. Ghezelayagh, W. Q. Heng, D. Nicolae, O. Fratu, R. Pop, G. Dilimot, V. Feies, P. Agache, R. Ruscu, M. lorgulescu, J. Gang, W. M. Lin, M. Lei, D. Z. Hui, and W. Tao, "A 0.13 μm CMOS SoCfor all format blue and red laser DVD front-end digital signal processor," in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf. (ISSCC 2006), pp. 1012-1021.
12. K. JooSeon, C. GoangSeog, P. HyunJeong, A. YoungJun, K. MyungSik, C. KiSun, L. TaeHo, H. MyungHee, B. JumHan, P. HyunSoo, L. YoonWoo, J. SooYul, S. JoongEon, and S. DongHo, "A 0.18 μm CMOS SoC of a front-end hardware platform for DVD-multi recorders," in Dig. Tech. Papers Int. Conf. Consum. Electron. (ICCE 2005), pp. 53-54.
13. H. Runsheng, N. Nazari, and S. Sutardja, "A DSP based receiver for 1000 BASE-T PHY," in Dig. Tech. Papers Solid-State Circuits Conf. (ISSCC 2001), p. 458.
14. H.-P. Lin, N. F. Chen, J.-T. Lai, and A.-Y. Wu, "1000 BASE-T Gigabit Ethernet baseband DSP IC design," in Proc. 2004 Int. Symp. Circuits Syst. (ISCAS '04), vol. 4, pp. IV-401-IV-404.
15. B. S. Leibowitz, J. Kizer, H. Lee, F. Chen, A. Ho, M. Jeeradit, A. Bansal, T. Greer, S. Li, R. Farjad-Rad, W. Stonecypher, Y. Frans, B. Daly, F. Heaton, B. W. Gariepp, C. W. Werner, N. Nguyen, V. Stojanovic, and J. L. Zerbe, "A 7.5 Gb/s 10-Tap DFE receiver with first Tap partial response, spectrally gated adaptation, and 2nd-Order data-filtered CDR," in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf. (ISSCC 2007), pp. 228-599.
16. J. F. Bulzacchelli, M. Meghelli, S. V. Rylov, W. Rhee, A. V. Rylyakov, H. A. Ainspan, B. D. Parker, M. P. Beakes, C. Aichin, T. J. Beukema, P. K. Pepeljugoski, L. Shan, Y. H. Kwark, S. Gowda, and D. J. Friedman, "A 10-Gb/s 5-Tap DFE/4-Tap FFE transceiver in 90-nm CMOS technology," IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2885-2900, Dec. 2006.
17. O. Tyschenko, A. Sheikholeslami, H. Tamura, Y. Tomita, H. Yamaguchi, M. Kibune, and T. Yamamoto, "A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65 nm CMOS," in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf. (ISSCC 2010), pp. 166-167.
18. H. Yamaguchi, H. Tamura, Y. Doi, Y. Tomita, T. Hamada, M. Kibune, S. Ohmoto, K. Tateishi, O. Tyschenko, A. Sheikholeslami, T. Higuchi, J. Ogawa, T. Saito, H. Ishida, and K. Gotoh, "A 5 Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65 nm CMOS," in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf. (ISSCC 2010), pp. 168-169.
19. H. Chung, A. Rylyakov, Z. T. Deniz, J. Bulzacchelli, W. Gu-Yeon, and F. Daniel, "A 7.5-GS/s 3.8-ENOB 52-mW flash ADC with clock duty cycle control in 65 nm CMOS," in Proc. Symp. VLSI Circuits, 2009, pp. 268-269.
20. K. Deguchi, N. Suwa, M. Ito, T. Kumamoto, and T. Miki, "A 6-bit 3.5-GS/s 0.9-V 98-mW flash ADC in 90-nm CMOS," IEEE J. Solid-State Circuits, vol. 43, no. 10, pp. 2303-2310, Oct. 2008.
21. M. Choi, J. Lee, J. Lee, and H. Son, "A 6-bit 5-GSample/s Nyquist A/D converter in 65 nm CMOS," in Proc. IEEE Symp. VLSI Circuits, Jun. 18-20, 2008, pp. 16-17.
22. P. Sunghyun, Y. Palaskas, and M. P. Flynn, "A 4-GS/s 4-bit flash ADC in 0.18 μm CMOS," IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 1865-1872, Sep. 2007.
23. M. El-Chammas and B. Murmann, "A 12-GS/s 81 mW 5-bit time-interleaved flash ADC with background timing skew calibration," in Proc. IEEE Symp. VLSI Circuits, 2010, pp. 157-158.
24. C.-C. Huang, C.-Y. Wang, and J.-T. Wu, "A CMOS 6-Bit 16-GS/s time-interleaved ADC with digital background calibration," in Proc. IEEE Symp. VLSI Circuits, 2010, pp. 159-160.
25. B. Verbruggen, J. Craninckx, M. Kuijk, P. Wambacq, and G. Van der Plas, "A 2.6 mW 6b 2.2 GS/s 4-times interleaved fully dynamic pipelined ADC in 40 nm digital CMOS," in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf. (ISSCC 2010), pp. 296-297.
26. A. Varzaghani and C.-K. K. Yang, "A 4.8 GS/s 5-bit ADC-based receiver with embedded DFE for signal equalization," IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 901-915, Mar. 2009.
27. A. Nazemi, C. Grace, L. Lewyn, B. Kobeissy, O. Agazzi, P. Voois, C. Abidin, G. Eaton, M. Kargar, C. Marquez, S. Ramprasad, F. Bollo, V. A. Posse, S. Wang, and G. Asmanis, "A 10.3 GS/s 6 bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90 nm CMOS," in Proc. IEEE Symp. VLSI Circuits, 2008, pp. 18-19.
28. Y. Greshishchev, J. Aguirre, M. Besson, R. Gibbins, C. Fait, P. Flemke, N. Ben-Hamida, D. Pollex, P. Schvan, and S.-C. Wang, "A 40 GS/s 6b ADC in 65 nm CMOS," in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf. (ISSCC 2010), pp. 390-391.
29. P. Schvan, J. Bach, C. Fait, P. Flemke, R. Gibbins, Y. Greshishchev, N. Ben-Hamida, D. Pollex, J. Sitch, W. Shing-Chi, and J. Wolczanski, "A 24 GS/s 6b ADC in 90 nm CMOS," in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf. (ISSCC 2008), pp. 544-634.
30. C.-K. K. Yang, V. Stojanovic, S. Modjtahedi, M. A. Horowitz, and W. F. Ellersick, "A serial-link transceiver based on 8-GSamples/s A/D and D/A converters in 0.25 μm CMOS," IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 1684-1692, Nov. 2001. (Pubitemid 33105932)
31. S. Galal and B. Razavi, "40-Gb/s amplifier and ESD protection circuit in 0.18 μm CMOS technology," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2389-2396, Dec. 2004.
32. E.-H. Chen, W. Leven, N. Warke, A. Joy, S. Hubbins, A. Amerasekera, Y. Ken, and Chih-Kong, "Adaptation of CDR and full scale range of ADC-based SerDes receiver," in Proc. Symp. VLSI Circuits, 2009, pp. 12-13.
33. J. L. Shin, K. Tam, D. Huang, B. Petrick, H. Pham, C. Hwang, H. Li, A. Smith, T. Johnson, F. Schumacher, D. Greenhill, A. S. Leon, and A. Strong, "A 40 nm 16-core 128-Thread CMT SPARC SoC processor," in Dig. Tech. Papers. IEEE Int. Solid-State Circuits Conf. (ISSCC 2010), pp. 98-99.
34. Y. Nakajima, A. Sakaguchi, T. Ohkido, T. Matsumoto, and M. Yotsuyanagi, "A self-background calibrated 6b 2.7 GS/s ADC with cascade-calibrated folding-interpolating architecture," in Proc. Symp. VLSI Circuits, 2009, pp. 266-267.
35. K. Mueller and M. Muller, "Timing recovery in digital synchronous data receivers," IEEE Trans. Commun., vol. 24, no. 5, pp. 516-531, May 1976.
36. T. Aboulnasr, M. Hage, B. Sayar, and S. Aly, "Characterization of a symbol rate timing recovery technique for a 2 B1Q digital receiver," IEEE Trans. Commun., vol. 42, no. 234, pp. 1409-1414, Feb.-Apr. 1994.
37. A. Emami-Neyestanak, S. Palermo, H.-C. Lee, and M. Horowitz, "CMOS transceiver with baud rate clock recovery for optical interconnects," in Dig. Tech. Papers Symp. VLSI Circuits, 2004, pp. 410-413.
38. F. A. Musa and A. C. Carusone, "Modeling and design of multilevel bang-bang CDRs in the presence of ISI and noise," IEEE Trans. Circuits Syst. I Reg. Papers, vol. 54, no. 10, pp. 2137-2147, Oct. 2007.
39. K.-L. J. Wong, C. E. Hung, and C.-K. K. Yang, "Edge and data adaptive equalization of serial-link transceivers," IEEE J. Solid-State Circuits, vol. 43, no. 9, pp. 2157-2169, Sep. 2008.
40. D. Sun, A. Xotta, and A. A. Abidi, "A 1 GHz CMOS analog front-end for a generalized PRML read channel," IEEE J. Solid-State Circuits, vol. 40, no. 11, pp. 2275-2285, Nov. 2005.
41. H. Noguchi, N. Yoshida, H. Uchida, M. Ozaki, S. Kanemitsu, and S. Wada, "A 40 Gb/s CDR with adaptive decision-point control using eye-opening-monitor feedback," in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf. (ISSCC 2008), 2008, pp. 228-609.
42. H.-M. Bae, J. B. Ashbrook, J. Park, N. R. Shanbhag, A. C. Singer, and S. Chopra, "An MLSE receiver for electronic dispersion compensation of OC-192 fiber links," IEEE J. Solid-State Circuits, vol. 41, no. 11, pp. 2541-2554, Nov. 2006.
43. E.-H. Chen, J. Ren, B. Leibowitz, H.-C. Lee, Q. Lin, K. Oh, F. Lambrecht, V. Stojanovic, J. Zerbe, and C.-K. K. Yang, "Near-optimal equalizer and timing adaptation for I/O links using a BER-based metric," IEEE J. Solid-State Circuits, vol. 43, no. 9, pp. 2144-2156, Sep. 2008.
44. H. Wu, J. A. Tierno, P. Pepeljugoski, J. Schaub, S. Gowda, J. A. Kash, and A. Hajimiri, "Integrated transversal equalizers in high-speed fiber-optic systems," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2131-2137, Dec. 2003.
45. X. Lin, J. Liu, H. Lee, and H. Liu, "A 2.5-to 3.5-Gb/s adaptive FIR equalizer with continuous-time wide-bandwidth delay line in 0.25-μm CMOS," IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1908-1918, Aug. 2006.
46. J. E. Jaussi, G. Balamurugan, D. R. Johnson, B. Casper, A. Martin, J. Kennedy, N. Shanbhag, and R. Mooney, "8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew," IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 80-88, Jan. 2005.
47. T.-C. Lee and B. Razavi, "A 125-MHz CMOS mixed-signal equalizer for Gigabit Ethernet on copper wire," in Proc. IEEE Custom Integr. Circuits Conf, 2001, pp. 131-134. (Pubitemid 32883625)
48. H. Chung and G.-Y. Wei, "Design-space exploration of backplane receivers with high-speed ADCs and digital equalization," in Proc. IEEE Custom Integr. Circuits Conf. (CICC '09), 2009, pp. 555-558.
49. S. Gondi and B. Razavi, "Equalization and clock and data recovery techniques for 10-Gb/s CMOS serial-link receivers," IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 1999-2011, Sep. 2007.
50. J.-H. Lu, K.-H. Chen, and S.-I. Liu, "A 10-Gb/s inductorless CMOS analog equalizer with an interleaved active feedback topology," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 2, pp. 97-101, Feb. 2009.
51. J. Poulton, R. Palmer, A. M. Fuller, T. Greer, J. Eyles, W. J. Dally, and M. Horowitz, "A 14-mW 6.25-Gb/s transceiver in 90-nm CMOS," IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2745-2757, Dec. 2007.
52. R. Reutemann, M. Ruegg, F. Keyser, J. Bergkvist, D. Dreps, T. Toifl, and M. Schmatz, "A 4.5 mW/Gb/s 6.4 Gb/s 22 + 1-lane source-synchronous link rx core with optional cleanup PLL in 65 nm CMOS," in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf. (ISSCC), 2010, pp. 160-161.
53. R. G. Gallager, Low-Density Parity-Check Codes. Cambridge, MA: MIT Press, 1963.
54. D. J. C. MacKay and R. M. Neal, "Near Shannon limit performance of low density parity check codes," Electron. Lett., vol. 32, no. 18, p. 1645, Aug. 1996.
55. Z. Zhengya, V. Anantharam, M. J. Wainwright, and B. Nikolic, "An efficient 10 GBASE-T Ethernet LDPC decoder design with low error floors," IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 843-855, Apr. 2010.
56. R. L. Narasimha and N. Shanbhag, "Forward error correction for highspeed I/O," in Proc. 42nd Asilomar Conf. Signals, Syst. Comput., Oct. 26, 2008, pp. 1513-1517.
57. D. Markovic, V. Stojanovic, B. Nikolic, M. A. Horowitz, and R. W. Brodersen, "Methods for true energy-performance optimization," IEEE J. Solid-State Circuits, vol. 39, no. 8, pp. 1282-1293, Aug. 2004.
58. Berkeley Predictive Technology Model [Online]. Available: http://www-device.eecs.berkeley.edu/~bsim3/bsim4.html
59. C.-K. K. Yang and E.-H. Chen, "ADC-based serial I/O receivers," in Proc. IEEE Custom Integr. Circuits Conf. (CICC '09), pp. 323-330.