Highly interleaved 5-bit, 250-MSample/s, 1.2-mW ADC with redundant channels in 65-nm CMOS

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 12, 2008, Pages 2641-2650

  Ginsburg, Brian P ^a   Chandrakasan, Anantha P ^b  

^a TEXAS INSTRUMENTS   (United States)

^b MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

ADC; Deep submicron CMOS; SAR; Time interleaving

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CLOCKS; JITTER; SYNTHETIC APERTURES;

ADC; ARCHITECTURAL SOLUTIONS; BIAS POINTS; CLOCK PARTITIONING; CORE VOLTAGES; DEEP SUBMICRON CMOS; DIE AREAS; HIGH SPEEDS; LOCAL VARIATIONS; LOW FREQUENCIES; NYQUIST; PARALLEL CIRCUITS; SAMPLING CLOCKS; SAMPLING NETWORKS; SAMPLING WINDOWS; SAR; SUCCESSIVE APPROXIMATION REGISTERS; SUPPLY VOLTAGES; TIME- INTERLEAVING; TOTAL POWERS; YIELD LOSSES;

MULTICARRIER MODULATION;

EID: 57849110638     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2006334     Document Type: Conference Paper

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