A 1.3-GHz 350-mW hybrid direct digital frequency synthesizer in 90-nm CMOS

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 9, 2010, Pages 1845-1855

  Yeoh, Hong Chang ^a   Jung, Jae Hun ^a   Jung, Yun Hwan ^a   Baek, Kwang Hyun ^a  

^a Chung Ang University   (South Korea)

Author keywords

CMOS direct digital frequency synthesizer (DDFS); digital to analog converter (DAC); pipelined accumulator; segmented nonlinear DAC

Indexed keywords

BOND PAD; CMOS CHIPS; DIGITAL-TO-ANALOG CONVERTERS; DIRECT DIGITAL FREQUENCY SYNTHESIZER; HYBRID DESIGN; LOW POWER; MAXIMUM OPERATING FREQUENCY; NONLINEAR DAC; NYQUIST FREQUENCY; PIPELINED ACCUMULATOR; SINE-WAVE; SPURIOUS FREE DYNAMIC RANGE;

CMOS INTEGRATED CIRCUITS; DC POWER TRANSMISSION; FREQUENCY SYNTHESIZERS; HYBRID COMPUTERS;

DIGITAL INTEGRATED CIRCUITS;

EID: 77956213079     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2056830     Document Type: Conference Paper

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