A 0.16pJ/conversion-step2.5mW1.25GS/s4b ADC in a 90nm digital CMOS process

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2006, Pages

  Van Der Plas, Geert ^a   Decoutere, Stefaan ^a   Donnay, Stéphane ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL CIRCUITS; ENERGY CONVERSION;

OFFSET-COMPENSATION SCHEME; SAMPLING RATE;

CMOS INTEGRATED CIRCUITS;

EID: 34547154701     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. IEEE 802.15 WPAN: www.ieee802.org/15/
2. D. Draxelmayr, "A 6b 600MHz 10mW ADC Array in Digital 90nm CMOS," ISSCC Dig. Tech. Papers, pp. 264-265, Feb., 2004.
3. A. Varzaghani and C-K. Yang, "A 600MS/S, 5-bit Pipelined Analog-to-Digital Converter for Serial-Link Applications," Symp. on VLSI Circuits Dig. Tech. Papers, pp. 276-279, June, 2004.
4. C. Sandner, et al., "A 6-bit 1.2-GS/s Low-Power Flash-ADC in 0.13-μm Digital CMOS", IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 1499-1505, July, 2005.
5. T. Kobayashi, et al., "A Current-Controlled Latch Sense Amplifier and a Static Power-Saving Input Buffer for Low-Power Architecture," IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 523-527, Apr., 1993.
6. M-J. E Lee, et al., "Low-Power Area-Efficient High-Speed I/O Circuit Techniques," IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1591-1599, Nov., 2000.