A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 5, 2005, Pages 1038-1046

  Grace, Carl R ^a,b   Hurst, Paul J ^c   Lewis, Stephen H ^c  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b ClariPhy Communications Inc   (United States)

^c University of California   (United States)

Author keywords

Adaptive systems; Analog to digital conversion; Bootstrapped calibration; CMOS analog integrated circuits; Digital background calibration

Indexed keywords

ADAPTIVE SYSTEMS; ALGORITHMS; AMPLIFIERS (ELECTRONIC); CALIBRATION; CMOS INTEGRATED CIRCUITS; DIGITAL COMMUNICATION SYSTEMS; DIGITAL TO ANALOG CONVERSION;

BOOTSTRAPPED CALIBRATION; CMOS ANALOG INTEGRATED CIRCUITS; DIGITAL BACKGROUND CALIBRATION; SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SNDR);

ANALOG TO DIGITAL CONVERSION;

EID: 18444378113     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.845972     Document Type: Article

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