A 1.5V 200MS/S 13b 25mW DAC with randomized nested background calibration in 0.13μm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 250-252

  Clara, Martin ^a   Klatzer, Wolfgang ^a   Seger, Berthold ^a   Di Giandomenico, Antonio ^a   Gori, Luca ^a  

^a INFINEON TECHNOLOGIES AUSTRIA AG   (Austria)

Author keywords

[No Author keywords available]

Indexed keywords

CALIBRATION; SPURIOUS SIGNAL NOISE;

CYCLIC BACKGROUND CALIBRATION;

CMOS INTEGRATED CIRCUITS;

EID: 34548847152     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373388     Document Type: Conference Paper

References (4)

1. W. Schofield, D. Mercer, and L. S. Onge, "A 16b 400MS/s DAC with <-80dBc IMD to 300MHz and <-160dBm/Hz Noise Power Spectral Density," ISSCC Dig. Tech. Papers, pp. 126-127, Feb., 2003.
2. Y. Cong and R. L. Geiger, "A 1.5-V 14-bit 100-MS/s Self-Calibrated DAC," IEEE J. Solid-State Circuits, vol. 38, pp. 2051-2060, Dec., 2003.
3. D. W. J. Groeneveld, H.J. Schowenaars, H.A.H. Termeer, et al., "A Self-Calibration Technique for Monolithic High-Resolution D/A Converters," IEEE J. Solid-State Circuits, vol. 24, pp. 1517-1522, Dec., 1989.
4. Q. Huang, P.A. Francese, C. Martelli, et al., "A200MS/s 14b 97mW DAC in 0.18μm CMOS," ISSCC Dig. Tech. Papers, pp. 364-365, Feb., 2004.