A single-bit 500 kHz-10 MHz multimode power-performance scalable 83-to-67 dB DR CT for SDR in 90 nm Digital CMOS

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 6, 2010, Pages 1159-1171

  Crombez, Pieter ^a   Van Der Plas, Geert ^a   Steyaert, Michiel S J ^b   Craninckx, Jan ^a  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

Continuous time ; Flexible; Low power; Multimode; Reconfigurable; Software defined radio

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; CONTINUOUS TIME SYSTEMS; ELECTRIC POWER UTILIZATION; ENERGY EFFICIENCY; LOW POWER ELECTRONICS; SOFTWARE RADIO;

CONTINUOUS-TIME; FLEXIBLE; LOW POWER; MULTIMODES; RECONFIGURABLE; SOFTWARE-DEFINED RADIOS;

BANDWIDTH;

EID: 77953265480     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2046230     Document Type: Article

References (34)

1. V. Giannini et al., "A 2 mm 0.1-to-5 GHz SDR receiver in 45 nm digital CMOS," in IEEE ISSCC Dig. Tech. Papers, Feb. 2009, pp. 407-408.
2. J. Cherry and W. M. Snelgrove, Continuous-Time Delta-Sigma Modulators for High Speed A/D Conversion: Theory, Practice and Fundamental Performance Limits. Boston, MA: Kluwer Academic, 1999.
3. M. Ortmanns and F. Gerfers, Continuous-Time Sigma-Delta A/D Conversion: Fundamentals, Performance Limits and Robust Implementations. New York, NY: Springer, 2005.
4. R. van Veldhoven, "A triple-mode continuous-time Sigma-Delta modulator with switched-capacitor feedback DAC for a GSM-EDGE/ CDMA2000/UMTS receiver," IEEE J. Solid-State Circuits, vol.38, no.12, pp. 2069-2076, Dec. 2003.
5. J. Arias et al., "A 32-mW 320-MHz continuous-time complex Delta- Sigma ADC for multi-mode wireless-LAN receivers," IEEE J. Solid- State Circuits, vol.41, no.2, pp. 339-351, Feb. 2006.
6. M. Vadipour et al., "A 2.1 mW/3.2 mW delay-compensated GSM/ WCDMA Sigma-Delta analog-digital converter," in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2008, pp. 180-181.
7. S. Ouzounov et al., "A 1.2 V 121-mode CT Delta-Sigma modulator for wireless receivers in 90 nm CMOS," in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 242-243.
8. V. Giannini, J. Craninckx, S. D'Amico, and A. Baschirotto, "Flexible baseband analog circuits for software-defined radio front-ends," IEEE J. Solid-State Circuits, vol.42, no.7, pp. 1501-1512, Jul. 2007.
9. P. Crombez, J. Craninckx, and M. Steyaert, "A 100 kHz-20 MHz reconfigurable Gm-C biquad low-pass filter in 0.13 μmCMOS," in Proc. IEEE A-SSCC, Nov. 2007, pp. 444-447.
10. P. Crombez, G. Van der Plas, M. Steyaert, and J. Craninckx, "A 500 kHz-10 MHz multimode power-performance scalable 83-to-67 dB DR CTΔΣ in 90 nm CMOS with flexible analog core circuitry," in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2009, pp. 70-71.
11. W. Yang et al., "A 100 mW 10 MHz-BW CT Delta-Sigma modulator with 87 dB DR and 91 dBc IMD," in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 498-499.
12. L. Breems, R. Rutten, R. van Veldhoven, G. van der Weide, and H. Termeer, "A 56 mW CT quadrature cascaded Sigma-Delta modulator with 77 dB DR in a near zero-IF 20 MHz band," in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 238-239.
13. G. Mitteregger et al., "A 14b 20mW640 MHz CMOS CT Delta-Sigma ADC with 20 MHz signal bandwidth and 12b ENOB," in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 62-63.
14. K. Reddy and S. Pavan, "A 20.7-mW continuous-time Delta-Sigma modulator with 15 MHz bandwidth and 70 dB dynamic range," in Proc. IEEE ESSCIRC, Sep. 2008, pp. 210-213.
15. S. Paton et al., "A 70-mW 300-MHz CMOS continuous-time Sigma- Delta ADC with 15-MHz bandwidth and 11 bits of resolution," IEEE J. Solid-State Circuits, vol.39, no.7, pp. 1056-1063, Jul. 2004.
16. M. Straayer and M. Perrott, "A 12-bit, 10-MHz bandwidth, continuoustime Sigma-Delta ADC with a 5-bit, 950-MS/s VCO-based quantizer," IEEE J. Solid-State Circuits, vol.43, no.4, pp. 805-814, Apr. 2008.
17. M. Park and M. Perrott, "A 0.13 μm CMOS 78 dB SNDR 87 mW 20 MHz BW CT Delta-Sigma ADC with VCO-based integrator and quantizer," in IEEE ISSCC Dig. Tech. Papers, Feb. 2009, pp. 170-171.
18. V. Dhanasekaran et al., "A 20 MHz BW 68 dB DR CT Delta-Sigma ADC based on a multi-bit time-domain quantizer and feedback element," in IEEE ISSCC Dig. Tech. Papers, Feb. 2009, pp. 174-175.
19. P. Crombez, G. Van der Plas, M. Steyaert, and J. Craninckx, "A single bit 6.8 mW 10 MHz power-optimized continuous-time ΔΣ with 67 dB DR in 90 nm CMOS," in Proc. IEEE ESSCIRC, Sep. 2009, pp. 336-339.
20. R. Schreier and G. Temes, Understanding Delta-Sigma Data Converters. Piscataway, NJ: IEEE Press, 2005.
21. M. Ortmanns, F. Gerfers, and Y. Manoli, "Compensation of finite gain-bandwidth induced errors in continuous-time Sigma-Delta modulators," IEEE Trans. Circuits Syst. I, vol.51, no.6, pp. 1088-1099, Jun. 2004.
22. J. Cherry and W. M. Snelgrove, "Excess loop delay in continuous-time Delta-Sigma modulators," IEEE Trans. Circuits Syst.II, vol.46, no.4, Apr. 1999.
23. M. Ortmanns, F. Gerfers, and Y. Manoli, "A continuous-time Sigma- Delta modulator with reduced sensitivity to clock jitter through SCR feedback," IEEE Trans. Circuits Syst. I, vol.52, no.5, pp. 875-884, May 2005.
24. G. Van der Plas, S. Decoutere, and S. Donnay, "A 0.16 pJ/conversionstep 2.5 mW 1.25 GS/s 4b ADC in a 90 nm digital CMOS process," in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 566-567.
25. P. Nuzzo et al., "A 10.6 mW/0.8 pJ power-scalable 1 GS/s 4b ADC in 0.18 μm CMOS with 5.8 GHz ERBW," in Proc. IEEE DAC, Jul. 2006, pp. 873-878.
26. S. Huang and Y. Lin, "A 1.2V 2 MHz BW0.084mm CT Delta-Sigma ADC with -97.7 dBc THD and 80 dB DR using low-latency DEM," in IEEE ISSCC Dig. Tech. Papers, Feb. 2009, pp. 172-173.
27. R. vanVeldhoven, R. Rutten, and L. Breems, "An inverter-based hybrid Sigma-Delta modulator," in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 492-493.
28. Y. Shu, B. Song, and K. Bacrania, "A 65 nm CMOS CT Delta-Sigma modulator with 81 dB DR and 8 MHz BW auto-tuned by pulse injection," in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 500-501.
29. S. Kulchycki, R. Trofin, K. Vleugels, and B. Wooley, "A 77-dB dynamic range, 7.5-MHz hybrid continuous-time/discrete-time cascaded Sigma-Delta modulator," IEEE J. Solid-State Circuits, vol.43, no.4, pp. 796-804, Apr. 2008.
30. T. Song, Z. Cao, and S. Yan, "A 2.7-mW 2-MHz continuous-time Sigma-Delta modulator with a hybrid active-passive loop filter," IEEE J. Solid-State Circuits, vol.43, no.2, pp. 330-341, Feb. 2008.
31. Z. Li and T. Fiez, "A 14 bit continuous-time Delta-Sigma A/D modulator with 2.5 MHz signal bandwidth," IEEE J. Solid-State Circuits, vol.42, no.9, pp. 1873-1883, Sep. 2007.
32. B. Bakkaloglu et al., "A 1.5-V multi-mode quad-band RF receiver for GSM/EDGE/CDMA2K in 90-nm digital CMOS process," IEEE J. Solid-State Circuits, vol.41, no.5, pp. 1149-1159, May 2006.
33. T. Caldwell and D. Johns, "A time-interleaved continuous-time Delta- Sigma modulator with 20-MHz signal bandwidth," IEEE J. Solid-State Circuits, vol.41, no.7, pp. 1578-1588, Jul. 2006.
34. M. Anderson and L. Sundstrom, "A 312-MHz CT Delta-Sigma modulator using a SC feedback DAC with reduced peak current," in Proc. IEEE ESSCIRC, Sep. 2007, pp. 240-243.