A 12-bit 320-MSample/s current-steering CMOS D/A converter in 0.44 mm 2

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 7, 2004, Pages 1064-1072

  O'Sullivan, Kevin ^a   Gorman, Chris ^b,c   Hennessy, Michael ^b,d   Callaghan, Vincent ^e  

^a Silicon and Software Systems   (Ireland)

^b Silicon and Software Systems   (Ireland)

^c EagleIC   (Ireland)

^d Analog Devices Inc UK   (United Kingdom)

^e Silicon and Software Systems   (Ireland)

Author keywords

CMOS; Digital to analog converter (DAC); Matching; Mixed analog digital integrated circuits

Indexed keywords

CMOS INTEGRATED CIRCUITS; DECODING; ELECTRIC CURRENTS; ENERGY UTILIZATION; FREQUENCIES; RESISTORS; SILICON;

MATCHING; MIXED ANALOG-DIGITAL INTEGRATED CIRCUITS; MOST SIGNIFICANT BITS (MSB); SPURIOUS FREE DYNAMIC RANGE (SFDR);

DIGITAL TO ANALOG CONVERSION;

EID: 3042819299     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.829923     Document Type: Conference Paper

References (14)

1. Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, and N. Yazawa, "A 10-b 70-MS/s CMOS D/A converter," IEEE J. Solid-State Circuits, vol. 26, pp. 637-642, Apr. 1991.
2. T. Wu, C. Jih, J. Chen, and C. Wu, "A low glitch 10-bit 75-MHz CMOS video D/A converter," IEEE J. Solid-State Circuits, vol. 30, pp. 68-72, Jan. 1995.
3. P. Hendriks, "Specifying communications DACs," IEEE Spectrum, vol. 34, pp. 57-69, July 1997.
4. 2," IEEE J. Solid-State Circuits, vol. 33, pp. 1948-1958, Dec. 1998.
5. A. Van den Bosch, M. Borremans, M. Steyaert, and W. Sansen, "A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter," IEEE J. Solid-State Circuits, vol. 36, pp. 315-323, Mar. 2001.
6. J. Bastos, A. Marques, M. Steyaert, and W. Sansen, "A 12-bit intrinsic accuracy high-speed CMOS DAC," IEEE J. Solid-State Circuits, vol. 33, pp. 1959-1968, Dec. 1998.
7. A. Van den Bosch, M. Borremans, M. Steyaert, and W. Sansen, "A 12 b 500 MSample/s current-steering CMOS D/A converter," in IEEE Int. Solid-State Circuits Dig. Tech. Papers, Feb. 2001, pp. 366-367.
8. 2 random walk CMOS DAC," IEEE J. Solid-State Circuits, vol. 34, pp. 1708-1717, Dec. 1999.
9. J. Hyde, T. Humes, C. Diorio, M. Thomas, and M. Figueroa, "A 300-MS/s 14-bit digital-to-analog converter in logic CMOS," IEEE J. Solid-State Circuits, vol. 38, pp. 734-740, May 2003.
10. C. C. Diaz, T. Ong, and J. Sun, "Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC era," IEEE J. Solid-State Circuits, vol. 38, pp. 444-449, Mar. 2003.
11. G. Scott, J. Lutze, M. Rubin, F. Nouri, and M. Manley, "NMOS drive current reduction caused by transistor layout and trench isolation induced stress," in IEEE Int. Electron Devices Meeting Tech. Dig., 1999, pp. 827-830.
12. A. Van den Bosch, M. Steyaert, and W. Sansen, "An accurate yield model for CMOS current-steering D/A converters," in Proc. IEEE Int. Symp. Circuits and Systems, 2000, pp. 105-108.
13. M. Pelgrom, A. Duinmaijer, and A. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol. SC-24, pp. 1433-1439, Oct. 1989.
14. B. Razavi, Principles of Data Conversion System Design. New York: IEEE Press, 1995.