500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 4, 2007, Pages 739-747

  Ginsburg, Brian P ^a,b   Chandrakasan, Anantha P ^a,b  

^a IEEE   (United States)

^b MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

ADC; Analog to digital conversion; Deep submicron CMOS; Successive approximation register; Ultra wideband radio

Indexed keywords

CAPACITOR ARRAYS; DEEP-SUBMICRON CMOS; SUCCESSIVE APPROXIMATION REGISTER (SAR); ULTRA-WIDEBAND RADIO;

ANALOG TO DIGITAL CONVERSION; CAPACITORS; ELECTRIC CURRENTS; NYQUIST DIAGRAMS; OPERATIONAL AMPLIFIERS;

CMOS INTEGRATED CIRCUITS;

EID: 33947675327     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.892169     Document Type: Article

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