A 14b 200MS/s DAC with SFDR>78dBc, IM3<-83dBc and NSD<-163dBm/Hz across the whole Nyquist band enabled by dynamic-mismatch mapping

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2010, Pages 151-152

  Tang, Yongjian ^a,b   Briaire, J ^b   Doris, Kostas ^b   Van Veldhoven, Robert ^a,b   Van Beek, Pieter ^a,b   Hegt, Hans ^a   Van Roermund, Arthur ^a  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

DAC; Mismatch; Timing error and calibration

Indexed keywords

CMOS DAC; CURRENT STEERING; DAC; DIGITAL CALIBRATIONS; DYNAMIC ELEMENT MATCHING; MISMATCH; NON-LINEARITY; NYQUIST BAND; STATE-OF-THE-ART PERFORMANCE; TIMING ERRORS;

CALIBRATION; MAPPING; TIME MEASUREMENT;

VLSI CIRCUITS;

EID: 77958007155     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2010.5560316     Document Type: Conference Paper

References (6)

1. Q. Huang, P.A. Francese, C. Martelli, J. Nielsen, "A 200MS/s 14b 97mW DAC in 0.18μm CMOS," ISSCC Dig. Tech. Papers, pp. 364-532, Feb., 2004.
2. M. Clara et al., "A 1.5V 200MS/s 13b 25mW DAC with Randomized Nested Background Calibration in 0.13μm CMOS," ISSCC Dig. Tech. Papers, pp. 250-251, Feb., 2007.
3. K. Rafeeque and V. Vasudevan, "A new technique for on-chip error estimation and reconfiguration of current-steering digital-to-analog converters," IEEE Trans. Circuits Syst. I, Reg. papers, vol.52, no.11, pp. 2348-2357, Nov., 2005.
4. K. Doris et al., "A 12b 500MS/s DAC with >70dB SFDR up to 120MHz in 0.18μm CMOS," ISSCC Dig. Tech. Papers, pp. 116-117, Feb., 2005.
5. K. Chan, J. Zhu and I. Galton, "A 150MS/s 14-bit Segmented DEM DAC with Greater than 83dB of SFDR Across the Nyquist band," Dig. Symp. VLSI Circuits, pp. 200-201, June, 2007.
6. R. van Veldhoven, "A Tri-Mode Continuous-Time ∑Δ Modulator with Switched-Capacitor Feedback DAC for a GSM-EDGE/CDMA2000/UMTS Receiver," ISSCC Dig. Tech. Papers, pp. 60-61, Feb., 2003.