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Volumn 53, Issue 9, 2006, Pages 848-852

Multibit Delta-Sigma Modulator With Two-Step Quantization and Segmented DAC

Author keywords

Analog; delta ( ) modulation; digital conversion quantization sigma

Indexed keywords

BINARY CODES; COMPUTER SIMULATION; DELTA SIGMA MODULATION; DIGITAL TO ANALOG CONVERSION; OPERATIONAL AMPLIFIERS;

EID: 34047187920     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2006.881825     Document Type: Article
Times cited : (24)

References (7)
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    • M. R. Miller and C. S. Petrie, “A multibit sigma-delta ADC for multimode receivers,” IEEE J. Solid-State Circuits, vol. 38, no. 3, pp. 475–482, Mar. 2003.
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    • Miller, M.R.1    Petrie, C.S.2
  • 2
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    • K. Vleugels, S. Rabii, and B. A. Wooley, “A 2.5 V sigma-delta modulator for broadband communication applications,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1887–1899, Dec. 2001.
    • (2001) IEEE J. Solid-State Circuits , vol.36 , Issue.12 , pp. 1887-1899
    • Vleugels, K.1    Rabii, S.2    Wooley, B.A.3
  • 3
    • 0026678367 scopus 로고
    • Multibit ΣΔ A/D converter incorporating a novel class of dynamic element matching techniques
    • Jan
    • B. H. Leung and S. Sutarja, “Multibit ΣΔ A/D converter incorporating a novel class of dynamic element matching techniques,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 39, no. 1, pp. 35-51,Jan. 1993.
    • (1993) IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process , vol.39 , Issue.1 , pp. 35-51
    • Leung, B.H.1    Sutarja, S.2
  • 4
    • 34047154909 scopus 로고    scopus 로고
    • A two-step quantization ΣΔ-modulator architecture with cascaded digital noise cancellation
    • Dec
    • S. Lindfors, “A two-step quantization ΣΔ-modulator architecture with cascaded digital noise cancellation,” in Proc. IEEE ICECS’00, Dec. 2000, vol. 1, pp. 125–128
    • (2000) in Proc. IEEE ICECS’00 , vol.1 , pp. 125-128
    • Lindfors, S.1
  • 5
    • 0031333312 scopus 로고    scopus 로고
    • A cascade sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR
    • Dec
    • T. L. Brooks, “A cascade sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR,” IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 1896–1905, Dec. 1997.
    • (1997) IEEE J. Solid-State Circuits , vol.32 , Issue.12 , pp. 1896-1905
    • Brooks, T.L.1
  • 6
    • 0026821719 scopus 로고
    • A high speed CMOS comparator with 8b resolution
    • Feb
    • G. M. Yin, F. O. Eynde, and W. Sansen, “A high speed CMOS comparator with 8b resolution,” IEEE J. Solid-State Circuits, vol. 27, no. 2, pp. 208–211, Feb. 1992.
    • (1992) IEEE J. Solid-State Circuits , vol.27 , Issue.2 , pp. 208-211
    • Yin, G.M.1    Eynde, F.O.2    Sansen, W.3
  • 7
    • 0032308948 scopus 로고    scopus 로고
    • A 113-dB SNR oversampling DAC with segmented noise-shaped scrambling
    • Dec
    • R. Adams, K. Nguyen, and K. Sweetland, “A 113-dB SNR oversampling DAC with segmented noise-shaped scrambling,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1871–1878, Dec. 1998.
    • (1998) IEEE J. Solid-State Circuits , vol.33 , Issue.12 , pp. 1871-1878
    • Adams, R.1    Nguyen, K.2    Sweetland, K.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.