A low-spurious low-power 12-bit 160-MS/s DAC in 90-nm CMOS for baseband wireless transmitter

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 3, 2007, Pages 486-495

  Seo, Dongwon ^a,b   McAllister, Gene H ^b  

^a IEEE   (United States)

^b QUALCOMM INC   (United States)

Author keywords

Degenerated current switch; Digital to analog converter (DAC); I Q mismatch; Package stress; Shaped centroid

Indexed keywords

DEGENERATED CURRENT SWITCHES; I/Q MISMATCH; PACKAGE STRESS; SHAPED CENTROID;

DIGITAL TO ANALOG CONVERSION; MICROPROCESSOR CHIPS; MOBILE COMPUTING; TRANSMITTERS;

CMOS INTEGRATED CIRCUITS;

EID: 33847738887     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.891722     Document Type: Article

References (20)

1. P. Hendriks, "Specifying communication DACs," IEEE Spectrum, vol. 34, pp. 58-69, Jul. 1997.
2. D. Seo, A high-speed and high-accuracy digital-to-analog converter Patent Application Pending, Qualcomm Inc., Sep. 2004.
3. J. Bastos, A. M. Marques, M. S. J. Steyaert, and W. Sansen, "A 12-bit intrinsic accuracy high-speed CMOS DAC," IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1959-1969, Dec. 1998.
4. 2," IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1948-1958, Dec. 1998.
5. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welebrs, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433-1439, Oct. 1989.
6. S. Luschas, R. Schreier, and H. Lee, "Radio frequency digital-to-analog converter," IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1462-1467, Sep. 2004.
7. W. Schofield, D. Mercer, and L. S. Onge, "A 16 b 400 MS/s DAC," in IEEE ISSCC Dig. Tech. Papers, 2003, pp. 1-10.
8. B. Scharferer and R. Adams, "A 3 V CMOS 400 mW 14 b 1.4 GS/s DAC for multi-carrier application," in IEEE ISSCC Dig. Tech. Papers, 2004, pp. 360-361.
9. H. Kohno et al., "A 10-bit 1-GSample/s Nyquist current steering CMOS D/A converter using a delayed driving scheme," in Proc. IEEE CICC, 1995, pp. 211-214.
10. R. Adams et al., "A 113 dB SNR oversampling DAC with segmented noise-shaped scrambling," in IEEE ISSCC Dig. Tech. Papers, 1998, pp. 62-63.
11. F. Carson and Y. Kim, "The development of a novel stacked package: package in package," in Proc. Electronics Manufacturing Technology Symp., Jul. 2004, pp. 91-96.
12. Y. G. Wang, D. B. Scott, J. Wu, J. L. Waller, J. Hu, K. Liu, and V. Ukraintsev, "Effects of uniaxial mechanical stress on drive current of 0.13 /spl mu/m MOSFETs," IEEE Trans. Electron Devices, vol. 50, no. 2, pp. 529-531, Feb. 2003.
13. R. C. Jaeger, R. Ramani, and J. Suhling, "Effects of stress-induced mismatches on CMOS analog circuits," in Proc. 1995 Int. VLSI TSA Symp., Taipei, Taiwan, May 1995, pp. 354-360.
14. R. C. Jaeger, J. C. Suhling, R. Ramini, A. T. Bradley, and J. Xu, "CMOS stress sensors on (100) silicon," IEEE J. Solid-State Circuits, vol. 35, no. 1, pp. 85-95, Jan. 2000.
15. R. C. Jaeger, R. Ramani, J. C. Suhling, and Y. Kang, "CMOS stress sensor circuits using piezoresistive field-effect transistors (PIFET's)," in Symp. VLSI Circuits Dig. Tech. Papers, 1995, pp. 43-44.
16. H. Mikoshiba, "Stress-sensitive properties of silicon-gate MOS devices," Solid State Electron., vol. 24, pp. 221-232, 1981.
17. B. Song, Advanced Analog IC Design. Urbana, IL: Dept. Electr. Comput. Eng., Univ. of Illinois, 1995.
18. Y.Nakamura, T. Miki, A. Maeda, H. Kondoh, and N. Yazawa, "A 10-b, 70-MS/s CMOS D/A converter," IEEE J. Solid-State Circuits, vol. 26, no. 4, pp. 637-642, Apr. 1991.
19. I. Polishchuk, N. Mathur, C. Sandstrom, P. Manos, and O. Pohland, "CMOS Vt-control improvement through implant lateral scatter elimination," in Proc. ISSM 2005, Sep. 2005, pp. 193-196.
20. C. Gallon, G. Reimbold, G. Ghibaudo, R. A. Blanchi, R. Gwoziecki, and C. Raynaud, "Electrical analysis of mechanical stress induced by shallow trench isolation [MOSFETs]," in Proc. 2003 ESSDERC, Sep. 2003, pp. 359-362.