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Volumn 55, Issue 10, 2008, Pages 2969-2979

Background calibration of pipelined ADCs via decision boundary gap estimation

Author keywords

Adaptive digital background calibration; Capacitor mismatch; Finite opamp gain; Pipelined analog to digital converter (ADC); Static nonlinearity

Indexed keywords

CALIBRATION; CODES (SYMBOLS); OPERATIONAL AMPLIFIERS; PIPELINES;

EID: 57149135074     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2008.925373     Document Type: Article
Times cited : (45)

References (27)
  • 1
    • 4644297975 scopus 로고    scopus 로고
    • Least mean square adaptive digital background calibration of pipelined analog-to-digital converter
    • Jan
    • Y. Chiu, C. W. Tsang, B. Nikolic, and P. R. Gray, "Least mean square adaptive digital background calibration of pipelined analog-to-digital converter," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 1, pp. 38-46, Jan. 2004.
    • (2004) IEEE Trans. Circuits Syst. I, Reg. Papers , vol.51 , Issue.1 , pp. 38-46
    • Chiu, Y.1    Tsang, C.W.2    Nikolic, B.3    Gray, P.R.4
  • 2
    • 0027853599 scopus 로고
    • A 15-b 1-msample/s digitally self-calibrated pipeline ADC
    • Dec
    • A. Karanicolas, H.-S. Lee, and K. Bacrania, "A 15-b 1-msample/s digitally self-calibrated pipeline ADC," IEEE J. Solid-State Circuits, vol. 28, no. 6, pp. 1207-1215, Dec. 1993.
    • (1993) IEEE J. Solid-State Circuits , vol.28 , Issue.6 , pp. 1207-1215
    • Karanicolas, A.1    Lee, H.-S.2    Bacrania, K.3
  • 4
    • 0021598441 scopus 로고
    • A ratio-independent algorithmic analog-to-digital conversion technique
    • Dec
    • P. Li, M. Chin, P. Gray, and R. Castello, "A ratio-independent algorithmic analog-to-digital conversion technique," IEEE J. Solid-State Circuits, vol. SSC-29, no. 6, pp. 828-836, Dec. 1984.
    • (1984) IEEE J. Solid-State Circuits , vol.SSC-29 , Issue.6 , pp. 828-836
    • Li, P.1    Chin, M.2    Gray, P.3    Castello, R.4
  • 5
    • 0024122160 scopus 로고
    • A 12-bit 1-msample/s capacitor error-averaging pipelined A/D converter
    • Dec
    • B.-S. Song, M. Tompsett, and K. Lakshmikumar, "A 12-bit 1-msample/s capacitor error-averaging pipelined A/D converter," IEEE J. Solid-State Circuits, vol. 33, no. 6, pp. 1316-1323, Dec. 1988.
    • (1988) IEEE J. Solid-State Circuits , vol.33 , Issue.6 , pp. 1316-1323
    • Song, B.-S.1    Tompsett, M.2    Lakshmikumar, K.3
  • 6
    • 0030421692 scopus 로고    scopus 로고
    • Statistical correction of A/D converter errors
    • Sep
    • T.-H. Shu, K. Bacrania, and C.-I. Chi, "Statistical correction of A/D converter errors," IEEE BCTM, pp. 189-191, Sep. 1996.
    • (1996) IEEE BCTM , pp. 189-191
    • Shu, T.-H.1    Bacrania, K.2    Chi, C.-I.3
  • 7
    • 0025449237 scopus 로고
    • Linearization of analog-to-digital converters
    • Jun
    • A. Dent and C. Cowan, "Linearization of analog-to-digital converters," IEEE Trans. Circuits Syst., vol. 37, pp. 729-737, Jun. 1990.
    • (1990) IEEE Trans. Circuits Syst , vol.37 , pp. 729-737
    • Dent, A.1    Cowan, C.2
  • 9
    • 51549106235 scopus 로고    scopus 로고
    • A cost-effective histogram test-based algorithm for digital calibration of high-precision pipelined ADCs
    • May
    • X. Dai, D. Chen, and R. Geiger, "A cost-effective histogram test-based algorithm for digital calibration of high-precision pipelined ADCs," in Proc. IEEE ISCAC, May 2005, vol. 5, pp. 4831-4834.
    • (2005) Proc. IEEE ISCAC , vol.5 , pp. 4831-4834
    • Dai, X.1    Chen, D.2    Geiger, R.3
  • 10
    • 37249009974 scopus 로고    scopus 로고
    • A digital self-calibration algorithm for ADCs based on histogram test using low-linearity input signals
    • May
    • L. Jin, D. Chen, and R. Geiger, "A digital self-calibration algorithm for ADCs based on histogram test using low-linearity input signals," in Proc. IEEE Int. Symp. Circuits Syst., May 2005, pp. 1378-1381.
    • (2005) Proc. IEEE Int. Symp. Circuits Syst , pp. 1378-1381
    • Jin, L.1    Chen, D.2    Geiger, R.3
  • 11
    • 0038380412 scopus 로고    scopus 로고
    • Digital background calibration of an algorithmic analog-to-digital converter using a simplified queue
    • Jun
    • E. Blecker, T.McDonald, O. Erdogan, P. Hurst, and S. Lewis, "Digital background calibration of an algorithmic analog-to-digital converter using a simplified queue," IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 1489-1497, Jun. 2003.
    • (2003) IEEE J. Solid-State Circuits , vol.38 , Issue.6 , pp. 1489-1497
    • Blecker, E.1    McDonald, T.2    Erdogan, O.3    Hurst, P.4    Lewis, S.5
  • 12
    • 0033893202 scopus 로고    scopus 로고
    • Gain error correction techinque for pipelined analog-to-digital converters
    • E. Siragusa and I. Galton, "Gain error correction techinque for pipelined analog-to-digital converters," Electron. Lett., vol. 36, pp. 617-618, 2000.
    • (2000) Electron. Lett , vol.36 , pp. 617-618
    • Siragusa, E.1    Galton, I.2
  • 13
    • 0141954044 scopus 로고    scopus 로고
    • Background calibration techniques for multistage pipelined adcs with digital redundancy
    • Sep
    • J. Li and U.-K. Moon, "Background calibration techniques for multistage pipelined adcs with digital redundancy," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 9, pp. 531-538, Sep. 2003.
    • (2003) IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process , vol.50 , Issue.9 , pp. 531-538
    • Li, J.1    Moon, U.-K.2
  • 14
    • 10444270157 scopus 로고    scopus 로고
    • A digitally enhanced 1.8-v 15-bit 40-msamples/sCMOS pipelined ADC
    • Dec
    • E. Siragusa and I. Galton, "A digitally enhanced 1.8-v 15-bit 40-msamples/sCMOS pipelined ADC," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2126-2138, Dec. 2004.
    • (2004) IEEE J. Solid-State Circuits , vol.39 , Issue.12 , pp. 2126-2138
    • Siragusa, E.1    Galton, I.2
  • 15
    • 0348233280 scopus 로고    scopus 로고
    • A 12-bit 75-ms/s pipelined ADC using open-loop residue amplification
    • Dec
    • B. Murmann and B. E. Boser, "A 12-bit 75-ms/s pipelined ADC using open-loop residue amplification," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2040-2050, Dec. 2003.
    • (2003) IEEE J. Solid-State Circuits , vol.38 , Issue.12 , pp. 2040-2050
    • Murmann, B.1    Boser, B.E.2
  • 17
    • 0033743496 scopus 로고    scopus 로고
    • True background calibration technique for pipelined ADC
    • Apr
    • S. Sonkusale, J. v. d. Spiegel, and K. Nagaraj, "True background calibration technique for pipelined ADC," Electron. Lett., vol. 26, pp. 786-788, Apr. 2000.
    • (2000) Electron. Lett , vol.26 , pp. 786-788
    • Sonkusale, S.1    Spiegel, J.V.D.2    Nagaraj, K.3
  • 18
    • 57149142532 scopus 로고    scopus 로고
    • Histogram based correction of matching errors in subranged ADC
    • Sep
    • J. Elbornsson and J.-E. Eklund, "Histogram based correction of matching errors in subranged ADC," in Proc. ESSCIRC 2001, Sep. 2001, pp. 555-558.
    • (2001) Proc. ESSCIRC 2001 , pp. 555-558
    • Elbornsson, J.1    Eklund, J.-E.2
  • 19
    • 4644296355 scopus 로고    scopus 로고
    • Online calibration of a nyquist-rate analog-to-digital converter using output code-density histograms
    • Jan
    • U. Eduri and F. Maloberti, "Online calibration of a nyquist-rate analog-to-digital converter using output code-density histograms," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 1, pp. 15-24, Jan. 2004.
    • (2004) IEEE Trans. Circuits Syst. I, Reg. Papers , vol.51 , Issue.1 , pp. 15-24
    • Eduri, U.1    Maloberti, F.2
  • 20
    • 57849161405 scopus 로고    scopus 로고
    • A zero-crossing based 8 bit, 200ms/s pipelined ADC
    • Dec
    • L. Brooks and H.-S. Lee, "A zero-crossing based 8 bit, 200ms/s pipelined ADC," IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2677-2687, Dec. 2007.
    • (2007) IEEE J. Solid-State Circuits , vol.43 , Issue.12 , pp. 2677-2687
    • Brooks, L.1    Lee, H.-S.2
  • 21
  • 22
    • 0030414371 scopus 로고    scopus 로고
    • A 2.5v, 12-b 5-MSample/s pipelined cmos adc
    • Dec
    • P. Yu and H.-S. Lee, "A 2.5v, 12-b 5-MSample/s pipelined cmos adc," IEEE J. Solid-State Circuits, vol. 31, pp. 1854-1861, Dec. 1996.
    • (1996) IEEE J. Solid-State Circuits , vol.31 , pp. 1854-1861
    • Yu, P.1    Lee, H.-S.2
  • 23
    • 33847714601 scopus 로고    scopus 로고
    • A 13-b linear, 40-MS/s pipelined ADC with self-configured capacitor matching
    • Mar
    • S. Ray and B.-S. Song, "A 13-b linear, 40-MS/s pipelined ADC with self-configured capacitor matching," IEEE J. Solid-State Circuits vol. 42, no. 3, pp. 463-474, Mar. 2007.
    • (2007) IEEE J. Solid-State Circuits , vol.42 , Issue.3 , pp. 463-474
    • Ray, S.1    Song, B.-S.2
  • 25
    • 4644246102 scopus 로고    scopus 로고
    • Signal recovery in time-interleaved analog-to-digital converters
    • V. Divi and G. Wornell, "Signal recovery in time-interleaved analog-to-digital converters," in Proc. IEEE ICASSP, 2004, pp. 593-596.
    • (2004) Proc. IEEE ICASSP , pp. 593-596
    • Divi, V.1    Wornell, G.2
  • 27
    • 0021586344 scopus 로고
    • Full-speed testing of A/D converters
    • Dec
    • J. Doernberg, H.-S. Lee, and D. Hodges, "Full-speed testing of A/D converters," IEEE J. Solid-State Circuits, vol. SSC-19, no. 6, pp. 820-827, Dec. 1984.
    • (1984) IEEE J. Solid-State Circuits , vol.SSC-19 , Issue.6 , pp. 820-827
    • Doernberg, J.1    Lee, H.-S.2    Hodges, D.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.