Laser fine-tuneable deep-submicrometer CMOS 14-bit DAC

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 55, Issue 8, 2008, Pages 2157-2165

  Marche, David ^a   Savaria, Yvon ^a   Gagnon, Yves ^b,c  

^a ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

^b LTRIM Technologies Inc   (Canada)

^c Intégration Dolphin   (Canada)

Author keywords

Analog integrated circuits; Calibration; CMOS; Data converter; Digital analog conversion (DAC); Laser trimming; Linearity; R2R ladder

Indexed keywords

ANALOG INTEGRATED CIRCUITS; CALIBRATION; CMOS INTEGRATED CIRCUITS; DIGITAL TO ANALOG CONVERSION; LADDERS; SYSTEM-ON-CHIP; TRIMMING;

CALIBRATION CIRCUITS; DATA CONVERTER; DIGITAL ANALOG CONVERSIONS (DAC); LASER TRIMMING; LEAST SIGNIFICANT BITS; LINEARITY; MOST SIGNIFICANT BIT; STANDARD CMOS PROCESS;

THIN FILM CIRCUITS;

EID: 54749117064     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2008.920152     Document Type: Article

References (41)

1. D. D. Buss, "Technology in the internet age," in Proc. Int. Solid-State Circuits Conf., 2002, pp. 18-21.
2. A. J. Annema, "Analog circuit in ultra-deep-submicron cmos," IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 132-143, Jan. 2005.
3. A. Hasting, The Art of Analog Layout. Upper Saddle River, NJ: Prentice-Hall, 2000.
4. L. Yu and R. Geiger, "Resistors layout for enhancing yield of r-2r dacs," in Proc. IEEE Int. Symp. Circuits Syst., May 2002, vol. 5, pp. 97-100.
5. n rotated walk switching scheme," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 11, pp. 1264-1268, Nov. 2006.
6. P. Stubberud and J. W. Bruce, "An analysis of dynamic element matching flash digital-to-analog converters, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 2, pp. 205-213, Feb. 2001.
7. K. Kato, T. Ono, and Y. Amemiya, "A monolithic 14-bit d/a converter fabricated with a new trimming technique (dot)," IEEE J. Solid-State Circuits, vol. SC-19, no. 5, pp. 734-740, Oct. 1984.
8. J. J. Price, "A passive laser-trimming technique to improve the linearity of a 10-bit D/A converter," IEEE J. Solid-State Circuits vol. SC-11, no. 6, pp. 789-794, Dec. 1976.
9. D. T. Comer, "A monolithic 12-bit DAC," IEEE Trans. Circuits Syst. vol. CAS-25, no. 7, pp. 504-509, Jul. 1978.
10. J. Hyde, T. Humes, C. Diorio, M. Thomas, and M. Figueroa, "A floating-gate trimmed, 14-bit, 250 Ms/s digital-to-analog converter in standard0.25- μm CMOS," in Proc. IEEE Symp. VLSI Circuits, Honolulu, HI, 2002, vol. 1, pp. 328-331.
11. A. Biman and D. G. Nairn, "Trimming of current mode DACs by adjusting Vt," in Proc. IEEE Int. Symp. Circuits Syst., Ma 1996, vol. 1, pp. 33-36.
12. J. R. Naylor, "A complete high-speed voltage output 16-bit monolithic DAC," IEEE J. Solid-State Circuits, vol. SC-18, no. 6, pp. 729-735, Dec. 1983.
13. T. Tobita and H. Takasago, "New trimming technology of a thick film resistor by pulse voltage method," IEEE Trans. Comput., Hybrids, Manufact. Technol., vol. 14, no. 3, pp. 613-617, Sep. 1991.
14. U.-K. Moon, G. C. Temes, and J. Steensgaard, "Digital techniques for improving the accuracy of data converters," IEEE Commun. Mag., pp. 136-143, Oct. 1999.
15. J. Pirkkalaniemi, M. Kosunen, M. Waltari, and K. Halonen, "A digital calibration for a 16-bit, 400-Mhz current-steering DAC," in Proc. IEEE Int. Symp. Circuits Syst., Vancouver, Canada, May 2004, vol. 1, pp. 297-299.
16. I. Galton, "Digital cancelation of D/A converter noise in pipelined A/D converters," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, pp. 185-196, Nov. 2000.
17. K. Parthasarathy, T. Kuyel, Z. Yu, D. Chen, and R. Geiger, "A 16-bit resistor string DAC with full-calibration at final test," in Proc. IEEE Int. Test Conf., 2005, pp. 1-10.
18. M. Meunier, Y. Gagnon, Y. Savaria, A. Lacourse, and M. Cadotte, "A novel laser trimming technique for microelectronics," Appl. Surface Sci., vol. 186, pp. 52-56, 2002.
19. L. Wang, Y. Fukatsu, and K. Watanabe, "A CMOS R2R ladder digital-to-analog converter and its characterization," IEEE Trans. Instrum. Meas., vol. 2, no. 5, pp. 1026-1031, May 2001.
20. M. P. Kennedy, "On the robustness of R2R ladder DACs," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 47, no. 2, pp. 109-116, Feb. 2000.
21. P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design. New York: McGraw-Hill, 1999.
22. M. Clara, A. Wiesbauer, and W. Klatzer, "Nonlinear distortion in current-steering D/A-converters due to assymetrical switching errors," in Proc. IEEE Int. Symp. Circuits Syst., Vancouver, Canada, May 2004, vol. 1, pp. 285-288.
23. T. Chen and G. G. E. Gielen, "The analysis and improvement of a current-steering DAC dynamic SFDR-I: The cell-dependent delay differences," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 1, pp. 3-15, Jan. 2006.
24. D. Marche, Y. Savaria, and Y. Gagnon, "A novel switch compensation technique for inverted R2R ladder DACs," in Proc. Int. Symp. Circuits Syst., May 2005, pp. 386-392.
25. Y. S. Park, H. C. Hyun, and S. Y. Kwang, "A 3.3 V-110 MHz 10-bit CMOS current-mode DAC," in IEEE Asia-Pacific Conf. ASIC, Aug. 2002, vol. 1, pp. 173-176.
26. B. Hyuen-Hee, Y. Jin-Sik, L. Myung-Jin, S. Eun-Seok, and L. Seung-Hoon, "A 3 V 12b 100 MS/s CMOS D/A converter for high-speed system applications," in Proc. Int. Symp. Circuits Syst., May 2003, vol. 1, pp. 869-872.
27. X. Weize and E. Friedman, "Clock feedthrough in CMOS analog transmission gate switches," in Proc. IEEE Int. ASIC/SOC Conf., Sep. 2002, pp. 181-185.
28. S. Rioux, A. Lacourse, Y. Savaria, and M. Meunier, "Design methods for CMOS low-current finely tunable voltage references covering a wide output range," in Proc. Int. Symp. Circuits Syst., May 2005, pp. 4257-4260.
29. LTRIM Technologies Inc.. Laval, QC, Canada, (Feb. 2007) [Online]. Available: http://www.ltrim.com
30. M. Burns and G. W. Roberts, An Introduction to Mixed-Signal IC Test and Measurment. New York: Oxford University Press, 2000.
31. L. Wang, Y. Fukatsu, and K. Watanabe, "Characterization of CMOS R2R ladder digital-to-analog converters," IEEE Trans. Instrum. Meas., vol. 50, pp. 1781-1786, Dec. 2001.
32. AD5554 Precision QUAD 14-Bit D/A Converter Analog Devices. Dallas, TX [Online]. Available: http://www.analog.com
33. Ltc1591 - 14-Bit Parallel Low Glitch Multiplying DAC With 4-Quadrant Resistors [Online]. Available: http://www.linear.com Linear Technology Corp.. Milpitas, CA
34. Y. Cong and T. L. Geiger, "A 1.5-V 14-Bit 100-MS/s Self-calibrated DAC," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2051-2059, Dec. 2003.
35. 2 CMOS DAC," IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1144-1147, Jul. 2001.
36. A. R. Bugeja and B.-S. Song, "A self-trimming 14-b 100-MS/s CMOS DAC," IEEE J. Solid-State Circuits, vol. 35, no. 7, pp. 1841-1852, Jul. 2000.
37. J. R. Naylor, "Testing digital/analog and analog/digital converters," in Proc. IEEE Int. Symp. Circuits Syst., Jul. 1978, vol. 25, pp. 526-538.
38. P. Prazak and T. Wang, "Superposition: The hidden DAC linearity error," Electron. Test, pp. 70-79, Jul. 1982.
39. Y. Gagnon, M. Meunier, and Y. Savaria, "Method and Apparatus for Iteratively, Selectively Tuning the Impedance of Integrated Semiconductor Devices Using a Focussed Heating Source," U.S. Patent # 09/332,059, Dec. 11, 2001.
40. A. Lacourse, H. Langlois, Y. Gagnon, and Y. Savaria, "Method for Modifying the Impedance of Semiconductor Devices Using a Focused Heating Source," U.S. Patent # 10/631,825, Mar. 25, 2005.
41. A. Lacourse, H. Langlois, H. St-Jean, Y. Gagnon, Y. Savaria, and M. Meunier, "A Tunable Semiconductor Component Provided With a Current Barrier," U.S. Patent # 11/431,610, May 11, 2006.