A low power 10 bit, 80 MS/s CMOS pipelined ADC at 1.8 v power supply

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 1, Issue , 2001, Pages 580-583

  Park, Yong In ^a   Karthikeyan, S ^a   Tsay, Frank ^a   Bartolome, Eduardo ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CIRCUIT DESIGN; CMOS PROCESS TECHNOLOGY; CMOS TRANSISTORS; DEEP SUB-MICRON; LOWER-POWER CONSUMPTION; REDUCED DYNAMICS; SYSTEM INTEGRATION; TOTAL POWER CONSUMPTION;

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; HAND HELD COMPUTERS; INTEGRATED CIRCUIT MANUFACTURE; AMPLIFIERS (ELECTRONIC); ANALOG TO DIGITAL CONVERSION; BANDWIDTH; COMPARATOR CIRCUITS; ELECTRIC POTENTIAL; OPERATIONAL AMPLIFIERS; SIGNAL TO NOISE RATIO; TRANSISTORS;

FLUIDIZED BED COMBUSTION; CMOS INTEGRATED CIRCUITS;

SIGNAL SWING; VOLTAGE SUPPLY;

EID: 0035016433     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.921922     Document Type: Conference Paper

References (6)

1. A. M. Abo and P. R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter", IEEE J. Solid-State Circuits, vol. 34, pp. 599-606, May, 1999.
2. D. G. Nairn, "A 10-bit, 3V, lOOMS/s Pipelined ADC", IEEE Custom Integrated Circuit Conference, pp. 257-260, May, 2000.
3. K. Y. Kim, N. Kusayanagi, and A. A. Abidi, "A 10-b, 100-MS/s CMOS A/D Converter", IEEE J. Solid-State Circuits, vol. 32, pp. 302-311, March 1997. (Pubitemid 127616587)
4. Thomas Cho, "Low power low voltage A/D conversion techniques using pipelined architecture", University of California Berkeley, Ph. D. thesis, 1995.
5. T. Cho and P. R. Gray, "A 10 b 20 Msamples/s, 35mW pipeline A/D converter", IEEE J. Solid-State Circuits, vol. 30, pp. 166-172, Mar. 1995.
6. K. Kusumoto, A. Matsuzawa, and K. Murata, "A 10b, 20Msamples/s, 35mW pipelined interpolating CMOS ADC. "IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 1200-1206, Dec. 1993.