A 10b 125MS/S 40mW pipelined ADC in 0.18μm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Yoshioka, Masato ^a   Kudo, Masahiro ^a   Gotoh, Kunihiko ^a   Watanabe, Yuu ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144436071     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. D. Miyazaki et al., "A 16mW 30MSample/s 10b Pipelined A/D Converter Using Pseudo Differential Architecture," ISSCC Dig. Tech. Papers, pp. 174-175, Feb., 2002.
2. B.-M. Min et al., "A 69mW 10b 80MS/s Pipelined CMOS ADC," ISSCC Dig. Tech. Papers, pp. 324-325, Feb., 2003.
3. K. Gotoh and O. Kobayashi, "3 States Logic Controlled CMOS Cyclic A/D Converter," Proc. CICC, pp. 366-369, May, 1986.
4. W. Bright, "8b 75MSample/s 70mW Parallel Pipelined ADC Incorporating Double Sampling," ISSCC Dig. Tech. Papers, pp. 146-147, Feb., 1998.