Multi-Bit Sigma Delta ADC with Reduced Feedback Levels, Extended Dynamic Range and Increased Tolerance for Analog Imperfections

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Volumn , Issue , 2007, Pages 77-80

  Wu, Jian Yi ^a   Subramoniam, Raj ^a   Zhang, Zhenyong ^a   Djabbari, Ali ^a   Holloway, Peter ^a   Maloberti, Franco ^b   Yousefi, Masood ^a   Aslan, Mehmet ^a   Hong, Hua ^a   Bahai, Ahmad ^a  

^a NATIONAL SEMICONDUCTOR CORPORATION   (United States)

^b UNIVERSITY OF PAVIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; DELTA MODULATION; DELTA SIGMA MODULATION; INTEGRATED CIRCUITS; MODULATORS; SPACE DIVISION MULTIPLE ACCESS;

DUAL GATE OXIDE; EXTENDED DYNAMIC RANGES; REDUCED FEEDBACKS; SAMPLING FREQUENCIES; SIGMA DELTA ADC; SIGMA-DELTA MODULATOR; SIGNAL BANDWIDTH; SIGNAL TO NOISE AND DISTORTION RATIO;

SIGNAL TO NOISE RATIO;

EID: 84938558904     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405685     Document Type: Conference Paper

References (5)

1. Jiang Yu and Franco Maloberti, " A low-power multi-bit SA modulator in 90-nm digital CMOS without DEM, " IEEE J. of Solid-State Circuits, vol. 40, no. 12, pp. 2428-2436, Dec. 2005
2. J. Silva, U. Moon, G. C. Temes, "Low-distortion delta-sigma topologies for MASH architectures", ISCAS Proceedings, pp. I-1144-7, May 2004
3. H Matsumoto and K. Watanabe, "Spike-Free Switched-Capacitor Circuits", Electron Letter, vol. 23, no. 8, pp. 428-429, April 1987.
4. Bastos, J.; Marques, A. M.; Steyaert, M. S. J.; Sansen, W., "A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC, IEEE J. of Solid-State Circuits, vol. 33, no. 12, pp. 1959-1969, Dec. 1998.
5. Ferragina, V.; Ghittori, N.; Maloberti, F.;" Low-power 6-bit flash ADC for high-speed data converters architectures", ISCAS 2006. Proceedings, pp. 3930-3933, May 2006