Design of a split-CLS pipelined ADC with full signal swing using an accurate but fractional signal swing opamp

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 12, 2010, Pages 2623-2633

  Hershberg, Benjamin ^a   Weaver, Skyler ^b   Moon, Un Ku ^c  

^a 1148 Kelley Engineering Center Corvallis   (United States)

^b OREGON STATE UNIVERSITY   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

A D; ADC; CBSC; CLS; comparator based switched capacitor circuit; correlated level shifting; dynamic zero crossing detector; pipelined analog to digital converter; scaled CMO Samplification technique; Split CLS; switched capacitor amplification; ZCBC; ZCD; zero crossing based circuit

Indexed keywords

A/D; ADC; CBSC; CLS; LEVEL-SHIFTING; PIPELINED ANALOG-TO-DIGITAL CONVERTER; SCALED CMO SAMPLIFICATION TECHNIQUE; SPLIT-CLS; SWITCHED CAPACITOR; SWITCHED CAPACITOR CIRCUITS; ZCBC; ZCD; ZERO-CROSSINGS;

AMPLIFICATION; ANALOG TO DIGITAL CONVERSION; CAPACITORS; COMPARATORS (OPTICAL); DATA STORAGE EQUIPMENT; DETECTORS; FREQUENCY CONVERTERS; MICROPROCESSOR CHIPS; OPERATIONAL AMPLIFIERS;

CROSSINGS (PIPE AND CABLE);

EID: 78650043578     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2073190     Document Type: Conference Paper

References (19)

1. P. R. Gray, P. J. Hurst, S. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated Circuits. New York: Wiley, 2001, pp. 425-452.
2. K. Bult and G. Geelen, "A fast-settling CMOS op amp for SC circuits with 90-dB DC gain", IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 1379-1384, Dec. 1990.
3. C. Yun, Gray, P. R. Gray, and B. Nikolic, "A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR", IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2139-2151, Dec. 2004.
4. B. Murmann and B. E. Boser, "A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification", IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2040-2050, Dec. 2003.
5. A. N. Karanicolas, H. S. Lee, and K. L. Barcrania, "A 15-b 1-Msample/s digitally self-calibrated pipeline ADC", IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1207-1215, Dec. 1993.
6. C. Enz and G. C. Temes, "Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization", Proc. IEEE, vol. 84, no. 11, pp. 1584-1614, Nov. 1996.
7. B. R. Gregoire and U. Moon, "An over-60 dB true rail-to-rail performance using correlated level shifting and an opamp with only 30 dB loop gain", IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2620-2630, Dec. 2008.
8. J. Hu, N. Dolev, and B. Murmann, "A 9.4-bit, 50-MS/s, 1.44-mW pipelined ADC using dynamic source follower residue amplification", IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1057-1066, Apr. 2009.
9. J. K. Fiorenza et al., "Comparator-based switched-capacitor circuits for scaled CMOS technologies", IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2658-2668, Dec. 2006.
10. L. Brooks and H. S. Lee, "A zero-crossing-based 8-bit 200 MS/s pipelined ADC", IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2677-2687, Dec. 2007.
11. L. Brooks and H. S. Lee, "A 12b, 50 MS/s, fully differential zerocrossing based pipelined ADC", IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3329-3343, Dec. 2009.
12. C. Liu et al., "A 10b 100 MS/s 1.13 mW SAR ADC with binary-scaled error compensation", in IEEE ISSCC 2010 Dig. Tech. Papers, Feb. 2010, pp. 386-387.
13. M. Yoshioka et al, "A 10b 50 MS/s 820 μW SAR ADC with on-chip digital calibration", in IEEE ISSCC 2010 Dig. Tech. Papers, Feb. 2010, pp. 384-385.
14. W. Liu, P. Huang, and Y. Chiu, "A 12b 22.5/45 MS/s 3.0 mW 0.059 mm CMOS SAR ADC achieving over 90 dB SFDR", in IEEE ISSCC 2010Dig. Tech. Papers, Feb. 2010, pp. 380-381.
15. C. T. Peach, U. Moon, and D. J. Allstot, "An 11.1 mW 42 MS/s 10 b ADC with two-step settling in 0.18 μm CMOS", IEEE J. Solid-State Circuits, vol. 45, no. 2, pp. 391-400, Feb. 2010.
16. D. A. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1997, p. 291.
17. M. Dessouky and A. Kaiser, "Very low-voltage digital-audio ΔSigma; modulator with 88-dB dynamic range using local switch bootstrapping", IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 349-355, Mar. 2001.
18. T. Musah and U. Moon, "Pseudo-differential zero-crossing-based circuit with differential error suppression", in Proc. ISCAS 2010, Jun. 2010, pp. 1731-1734.
19. B. Hershberg, S. Weaver, and U. Moon, "A 1.4 V signal swing hybrid CLS-opamp/ZCBC pipelined ADC using a 300 mV output swing opamp", in IEEE ISSCC 2010 Dig. Tech. Papers, Feb. 2010, pp. 302-303.