A 1.2V 2MHz BW 0.084mm2 CT Δσ ADC with-97.7dBc THD and 80dB DR using low-latency DEM

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages 172-174

  Huang, Sheng Jui ^a   Lin, Yung Yu ^a  

^a MEDIATEK INC   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349282145     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977363     Document Type: Conference Paper

References (6)

1. W. Yang et al., "A 100mW 10MHz-BW CT Δσ Modulator with 87dB DR and 91dBc IMD," ISSCC Dig. Tech. Papers, pp. 498-499, Feb. 2008.
2. L. Dörrer et al., "A 3mW 74dB SNR 2MHz CT Δσ ADC with a Tracking-ADC-Quantizer in 0.13μm CMOS, '' ISSCC Dig. Tech. Papers, pp. 492-493, Feb. 2005.
3. G. Mitteregger et al., "A 14b 20mW 640MHz CMOS CT Δσ ADC with 20MHz Signal BW and 12b ENOB," ISSCC Dig. Tech. Papers, pp. 62-63, Feb. 2006
4. R. van Veldhoven, "A Tri-Mode Continuous-Time Δσ Modulator with Switched- Capacitor Feedback DAC for a GSM-EDGE/CDMA2000/UMTS Receiver," ISSCC Dig. Tech. Papers, pp. 60-61, Feb. 2003.
5. S. Ouzounov et al., "A 1.2V 121-Mode CT Δσ Modulator for Wireless Receiver in 90nm CMOS," ISSCC Dig. Tech. Papers, pp. 242-243, Feb. 2007.
6. V.V. Ivanov, I.M. Filanovsky, Operational Amplifier Speed and Accuracy Improvement, Kluwer Academic Publishers, Boston.