-
2
-
-
77955218036
-
-
McGraw-Hill, NY
-
Lau, J. H., C. K. Lee, C. S. Premachandran, A. Yu, Advanced MEMS Packaging, McGraw-Hill, NY, 2010.
-
(2010)
Advanced MEMS Packaging
-
-
Lau, J.H.1
Lee, C.K.2
Premachandran, C.S.3
Yu, A.4
-
3
-
-
0000793139
-
Cramming More Components onto Integrated Circuits
-
April 19
-
Gordon Moore, "Cramming More Components Onto Integrated Circuits", Electronics, Vol. 38, No. 8, April 19, 1965.
-
(1965)
Electronics
, vol.38
, Issue.8
-
-
Moore, G.1
-
4
-
-
79956077641
-
Overview and Outlook of TSV and 3D Integrations
-
Lau, J. H., "Overview and Outlook of TSV and 3D Integrations", Journal of Microelectronics International, V.28, No. 2, 2011, pp. 8-22.
-
(2011)
Journal of Microelectronics International
, vol.28
, Issue.2
, pp. 8-22
-
-
Lau, J.H.1
-
5
-
-
84856477314
-
Embedded 3D Hybrid IC Integration Systemin-Package (SiP) for Opto-Electronic Interconnects in Organic Substrates
-
in press
-
Lau, J. H., M. S. Zhang, and S. W. R. Lee, "Embedded 3D Hybrid IC Integration Systemin-Package (SiP) for Opto-Electronic Interconnects in Organic Substrates", ASME Transactions, Journal of Electronic Packaging (in press, 2011).
-
(2011)
ASME Transactions, Journal of Electronic Packaging
-
-
Lau, J.H.1
Zhang, M.S.2
Lee, S.W.R.3
-
6
-
-
79951902080
-
Critical Issues of 3D IC Integrations
-
Lau, J. H., "Critical Issues of 3D IC Integrations", IMAPS Transactions, Journal of Microelectronics and Electronic Packaging, First Quarter Issue, 2010, pp. 35-43.
-
(2010)
IMAPS Transactions, Journal of Microelectronics and Electronic Packaging, First Quarter Issue
, pp. 35-43
-
-
Lau, J.H.1
-
7
-
-
84856484569
-
Design and Process of 3D MEMS Packaging
-
Lau, J. H., "Design and Process of 3D MEMS Packaging", IMAPS Transactions, Journal of Microelectronics and Electronic Packaging, First Quarter Issue, 2010, pp. 10-15.
-
(2010)
IMAPS Transactions, Journal of Microelectronics and Electronic Packaging, First Quarter Issue
, pp. 10-15
-
-
Lau, J.H.1
-
8
-
-
77952599293
-
3D LED and IC Wafer Level Packaging
-
Lau, J. H., Lee, R., Yuen, M., and Chan, P., "3D LED and IC Wafer Level Packaging", Journal of Microelectronics International, Vol. 27, Issue 2, 2010, pp. 98-105.
-
(2010)
Journal of Microelectronics International
, vol.27
, Issue.2
, pp. 98-105
-
-
Lau, J.H.1
Lee, R.2
Yuen, M.3
Chan, P.4
-
9
-
-
79951892774
-
State-of-the-art and Trends in 3D Integration
-
March/April
-
Lau, J. H., "State-of-the-art and Trends in 3D Integration", Chip Scale Review, March/April, 2010, pp. 22-28.
-
(2010)
Chip Scale Review
, pp. 22-28
-
-
Lau, J.H.1
-
10
-
-
77955205984
-
TSV Manufacturing Yield and Hidden Costs for 3D IC Integration
-
Lau, J. H., "TSV Manufacturing Yield and Hidden Costs for 3D IC Integration", IEEE Proceedings of ECTC, Las Vegas, NV, June 2010, pp. 1031-1041.
-
IEEE Proceedings of ECTC, Las Vegas, NV, June 2010
, pp. 1031-1041
-
-
Lau, J.H.1
-
11
-
-
79951910180
-
3D IC Integration with TSV Interposers for High-Performance Applications
-
September/October
-
Lau, J. H., Y. S. Chan, and R. S. W. Lee, "3D IC Integration with TSV Interposers for High-Performance Applications", Chip Scale Review, September/October, 2010, pp. 26-29.
-
(2010)
Chip Scale Review
, pp. 26-29
-
-
Lau, J.H.1
Chan, Y.S.2
Lee, R.S.W.3
-
12
-
-
70349686526
-
Study of 15-μm-pitch solder microbumps for 3D IC integration
-
Yu, A., J. H. Lau, Ho, S., Kumar, A., Wai, Y., Yu, D., Jong, M., Kripesh, V., Pinjala, D., Kwong, D., "Study of 15-μm-pitch solder microbumps for 3D IC integration." IEEE Proceedings of ECTC, San Diego, CA, May 2009, pp. 6 -10.
-
IEEE Proceedings of ECTC, San Diego, CA, May 2009
, pp. 6-10
-
-
Yu, A.1
Lau, J.H.2
Ho, S.3
Kumar, A.4
Wai, Y.5
Yu, D.6
Jong, M.7
Kripesh, V.8
Pinjala, D.9
Kwong, D.10
-
13
-
-
70349659227
-
Three dimensional interconnects with high aspect ratio TSVs and fine pitch solder microbumps
-
Also, accepted for publication in IEEE Transactions in Advanced Packaging
-
Yu, A., J. H. Lau, Ho, S., Kumar, A., Yin, H., Ching, J., Kripesh, V., Pinjala, D., Chen, S., Chan, C., Chao, C., Chiu, C., Huang, M., and Chen, C., "Three dimensional interconnects with high aspect ratio TSVs and fine pitch solder microbumps." IEEE Proceedings of ECTC, San Diego, CA, May 2009, pp. 350-354. Also, accepted for publication in IEEE Transactions in Advanced Packaging.
-
IEEE Proceedings of ECTC, San Diego, CA, May 2009
, pp. 350-354
-
-
Yu, A.1
Lau, J.H.2
Ho, S.3
Kumar, A.4
Yin, H.5
Ching, J.6
Kripesh, V.7
Pinjala, D.8
Chen, S.9
Chan, C.10
Chao, C.11
Chiu, C.12
Huang, M.13
Chen, C.14
-
14
-
-
63049114343
-
Development of Fine Pitch Solder Microbumps for 3D Chip Stacking
-
Also, accepted for publication in IEEE Transactions in Advanced Packaging
-
Yu, A., A. Kumar, S. Ho, H. Yin, J. H. Lau, Ching, J., Kripesh, V., Pinjala, D., Chen, S., Chan, C., Chao, C., Chiu, C., Huang, M., and Chen, C., "Development of Fine Pitch Solder Microbumps for 3D Chip Stacking", IEEE EPTC Proceedings, Singapore, December 2008, pp. 387-392. Also, accepted for publication in IEEE Transactions in Advanced Packaging.
-
IEEE EPTC Proceedings, Singapore, December 2008
, pp. 387-392
-
-
Yu, A.1
Kumar, A.2
Ho, S.3
Yin, H.4
Lau, J.H.5
Ching, J.6
Kripesh, V.7
Pinjala, D.8
Chen, S.9
Chan, C.10
Chao, C.11
Chiu, C.12
Huang, M.13
Chen, C.14
-
15
-
-
70349299917
-
Development of silicon carriers with embedded thermal solutions for high power 3-D package
-
September
-
Yu, A., N. Khan, G. Archit, D. Pinjalal, K. Toh, V. Kripesh, S. Yoon, and J. H. Lau, "Development of silicon carriers with embedded thermal solutions for high power 3-D package." IEEE Transactions on Components and Packaging Technology, Vol. 32, No. 3, September 2009, pp. 566-571.
-
(2009)
IEEE Transactions on Components and Packaging Technology
, vol.32
, Issue.3
, pp. 566-571
-
-
Yu, A.1
Khan, N.2
Archit, G.3
Pinjalal, D.4
Toh, K.5
Kripesh, V.6
Yoon, S.7
Lau, J.H.8
-
16
-
-
77949562449
-
Integrated Liquid Cooling Systems for 3-D Stacked TSV Modules
-
Tang, G., O. Navas, D. Pinjala, J. H. Lau, A. Yu, and V. Kripesh, "Integrated Liquid Cooling Systems for 3-D Stacked TSV Modules", IEEE Transactions on Components and Packaging Technologies, Vol. 33, Issue 1, 2010, pp. 184-195.
-
(2010)
IEEE Transactions on Components and Packaging Technologies
, vol.33
, Issue.1
, pp. 184-195
-
-
Tang, G.1
Navas, O.2
Pinjala, D.3
Lau, J.H.4
Yu, A.5
Kripesh, V.6
-
17
-
-
71049162943
-
C2W Bonding Method for MEMS Applications
-
Chen, K., C. Premachandran, K. Choi, C. Ong, X. Ling, A. Khairyanto, B. Ratmin, P. Myo, and J. H. Lau, "C2W Bonding Method for MEMS Applications", IEEE Proceedings of ECTC, December 2008, pp. 1283-1287.
-
IEEE Proceedings of ECTC, December 2008
, pp. 1283-1287
-
-
Chen, K.1
Premachandran, C.2
Choi, K.3
Ong, C.4
Ling, X.5
Khairyanto, A.6
Ratmin, B.7
Myo, P.8
Lau, J.H.9
-
18
-
-
51449095637
-
A Novel, Wafer-Level Stacking Method for Low-Chip Yield and Non-Uniform, Chip-Size Wafers for MEMS and 3D SIP Applications
-
Premachandran, C. S., J. H. Lau, X. Ling, A. Khairyanto, K. Chen, and Myo Ei Pa Pa,, "A Novel, Wafer-Level Stacking Method for Low-Chip Yield and Non-Uniform, Chip-Size Wafers for MEMS and 3D SIP Applications", IEEE Proceedings of ECTC, Orlando, FL, May 27-30, 2008, pp. 314-318.
-
IEEE Proceedings of ECTC, Orlando, FL, May 27-30, 2008
, pp. 314-318
-
-
Premachandran, C.S.1
Lau, J.H.2
Ling, X.3
Khairyanto, A.4
Chen, K.5
Myo, E.P.P.6
-
19
-
-
70349658299
-
Development of Through Silicon Via (TSV) Interposer Technology for Large Die (21x21mm) Finepitch Cu/low-k FCBGA Package
-
Also, IEEE Transactions on CPMT (in press.)
-
Zhang, X., T. Chai, J. H. Lau, C. Selvanayagam, K. Biswas, S. Liu, D. Pinjala, G. Tang, Y. Ong, S. Vempati, E. Wai, H. Li, B. Liao, N. Ranganathan, V. Kripesh, J. Sun, J. Doricko, and C. Vath, "Development of Through Silicon Via (TSV) Interposer Technology for Large Die (21x21mm) Finepitch Cu/low-k FCBGA Package", IEEE Proceedings of ECTC, May, 2009, pp. 305-312. Also, IEEE Transactions on CPMT (in press.)
-
IEEE Proceedings of ECTC, May, 2009
, pp. 305-312
-
-
Zhang, X.1
Chai, T.2
Lau, J.H.3
Selvanayagam, C.4
Biswas, K.5
Liu, S.6
Pinjala, D.7
Tang, G.8
Ong, Y.9
Vempati, S.10
Wai, E.11
Li, H.12
Liao, B.13
Ranganathan, N.14
Kripesh, V.15
Sun, J.16
Doricko, J.17
Vath, C.18
-
20
-
-
77950959311
-
Effect of TSV Interposer on the Thermal Performance of FCBGA Package
-
Hoe, G., G. Tang, P. Damaruganath, C. Chong, J. H. Lau, X. Zhang, and K. Vaidyanathan, "Effect of TSV Interposer on the Thermal Performance of FCBGA Package", IEEE Proceedings of Electronics Packaging and Technology Conference, Singapore, December 2009, pp. 778-786.
-
IEEE Proceedings of Electronics Packaging and Technology Conference, Singapore, December 2009
, pp. 778-786
-
-
Hoe, G.1
Tang, G.2
Damaruganath, P.3
Chong, C.4
Lau, J.H.5
Zhang, X.6
Vaidyanathan, K.7
-
21
-
-
70349693680
-
Development of Novel Intermetallic Joints using Thin Film Indium Based Solder by Low Temperature Bonding Technology for 3D IC Stacking
-
Choi, W. O., C. S. Premachandran, S. Ong, Ling, X., E. Liao, K. Ahmad, B. Ratmin, K. Chen, P. Thaw, and J. H. Lau, "Development of Novel Intermetallic Joints using Thin Film Indium Based Solder by Low Temperature Bonding Technology for 3D IC Stacking", IEEE Proceedings of ECTC, San Diego, CA, May, 2009, pp. 333-338.
-
IEEE Proceedings of ECTC, San Diego, CA, May, 2009
, pp. 333-338
-
-
Choi, W.O.1
Premachandran, C.S.2
Ong, S.3
Ling, X.4
Liao, E.5
Ahmad, K.6
Ratmin, B.7
Chen, K.8
Thaw, P.9
Lau, J.H.10
-
22
-
-
79951937106
-
Evaluation of Stresses in Thin Device Wafer using Piezoresistive Stress Sensor
-
and IEEE Transactions in Components and Packaging Technologies, (in press.)
-
Kumar, A., X. Zhang, Q. Zhang, M. Jong, G. Huang, V. Kripesh, C. Lee, J. H. Lau, D. Kwong, V. Sundaram, R. Tummula, and M. Georg (2008), "Evaluation of Stresses in Thin Device Wafer using Piezoresistive Stress Sensor," IEEE Proceedings of EPTC, December, pp. 1270-1276, and IEEE Transactions in Components and Packaging Technologies, (in press.)
-
(2008)
IEEE Proceedings of EPTC, December
, pp. 1270-1276
-
-
Kumar, A.1
Zhang, X.2
Zhang, Q.3
Jong, M.4
Huang, G.5
Kripesh, V.6
Lee, C.7
Lau, J.H.8
Kwong, D.9
Sundaram, V.10
Tummula, R.11
Georg, M.12
-
23
-
-
70349670743
-
Development of 3-D Silicon Die Stacked Package Using Flip Chip Technology with Micro Bump Interconnects
-
Also, accepted for publication in IEEE Transactions in CPMT
-
Vempati1, S. R., S. Nandar, C. Khong, Y. Lim, K. Vaidyanathan, J. H. Lau, B. P. Liew, K. Y. Au, S. Tanary, A. Fenne, R. Erich, and J. Milla, "Development of 3-D Silicon Die Stacked Package Using Flip Chip Technology with Micro Bump Interconnects", IEEE Proceedings of ECTC San Diego, CA, May, 2009, pp. 980-987. Also, accepted for publication in IEEE Transactions in CPMT.
-
IEEE Proceedings of ECTC San Diego, CA, May, 2009
, pp. 980-987
-
-
Vempati, S.R.1
Nandar, S.2
Khong, C.3
Lim, Y.4
Vaidyanathan, K.5
Lau, J.H.6
Liew, B.P.7
Au, K.Y.8
Tanary, S.9
Fenne, A.10
Erich, R.11
Milla, J.12
-
24
-
-
70349663697
-
3D Packaging with Through Silicon Via (TSV) for Electrical and Fluidic Interconnections
-
Khan, N., L. Yu, P. Tan, S. Ho, N. Su, H. Wai, K. Vaidyanathan, D. Pinjala, J. H. Lau, T. Chuan, "3D Packaging with Through Silicon Via (TSV) for Electrical and Fluidic Interconnections", IEEE Proceedings of ECTC, San Diego, CA, May, 2009, pp. 1153-1158.
-
IEEE Proceedings of ECTC, San Diego, CA, May, 2009
, pp. 1153-1158
-
-
Khan, N.1
Yu, L.2
Tan, P.3
Ho, S.4
Su, N.5
Wai, H.6
Vaidyanathan, K.7
Pinjala, D.8
Lau, J.H.9
Chuan, T.10
-
25
-
-
51349133304
-
Effect of Wafer Back Grinding on the Mechanical Behavior of Multilayered Low-k for 3D-Stack Packaging Applications
-
Also, IEEE Transactions on Components and Packaging Technologies (in press)
-
Sekhar, V. N., S. Lu, A. Kumar, T. C. Chai, V. Lee, S. Wang, X. Zhang, C. S. Premchandran, V. Kripesh, and J. H. Lau, "Effect of Wafer Back Grinding on the Mechanical Behavior of Multilayered Low-k for 3D-Stack Packaging Applications", IEEE Proceedings of Electronic, Components & Technology Conference, Orlando, FL, May 27-30, 2008, pp. 1517-1524. Also, IEEE Transactions on Components and Packaging Technologies (in press).
-
IEEE Proceedings of Electronic, Components & Technology Conference, Orlando, FL, May 27-30, 2008
, pp. 1517-1524
-
-
Sekhar, V.N.1
Lu, S.2
Kumar, A.3
Chai, T.C.4
Lee, V.5
Wang, S.6
Zhang, X.7
Premchandran, C.S.8
Kripesh, V.9
Lau, J.H.10
-
26
-
-
51349164996
-
Development of 3D Silicon Module with TSV for System in Packaging
-
Khan, N., V. Rao, S. Lim, S. Ho, V. Lee, X. Zhang, R. Yang, E. Liao, Ranganathan, T. Chai, V. Kripesh, and J. H. Lau, "Development of 3D Silicon Module with TSV for System in Packaging", IEEE Proceedings of Electronic, Components & Technology Conference, Orlando, FL, May 27-30, 2008, pp. 550-555.
-
IEEE Proceedings of Electronic, Components & Technology Conference, Orlando, FL, May 27-30, 2008
, pp. 550-555
-
-
Khan, N.1
Rao, V.2
Lim, S.3
Ho, S.4
Lee, V.5
Zhang, X.6
Yang, R.7
Liao, E.8
Ranganathan9
Chai, T.10
Kripesh, V.11
Lau, J.H.12
-
27
-
-
51349094381
-
High RF Performance TSV for Silicon Carrier for High Frequency Application
-
Ho, S., S. Yoon, Q. Zhou, K. Pasad, V. Kripesh and J. H. Lau, "High RF Performance TSV for Silicon Carrier for High Frequency Application", IEEE Proceedings of Electronic, Components & Technology Conference, Orlando, FL, May 27-30, 2008, pp. 1956-1952.
-
IEEE Proceedings of Electronic, Components & Technology Conference, Orlando, FL, May 27-30, 2008
, pp. 1956-11952
-
-
Ho, S.1
Yoon, S.2
Zhou, Q.3
Pasad, K.4
Kripesh, V.5
Lau, J.H.6
-
28
-
-
63049096701
-
Process Development and Reliability of Microbumps
-
Also, accepted for the IEEE Transactions in Components and Packaging Technology
-
Lim, S., V. Rao, H. Yin, W. Ching, V. Kripesh, C. Lee, J. H. Lau, J. Milla and A. Fenner, "Process Development and Reliability of Microbumps," IEEE Proceedings of Electronic Packaging Technology Conference, December 2008, pp. 367-372. Also, accepted for the IEEE Transactions in Components and Packaging Technology.
-
IEEE Proceedings of Electronic Packaging Technology Conference, December 2008
, pp. 367-372
-
-
Lim, S.1
Rao, V.2
Yin, H.3
Ching, W.4
Kripesh, V.5
Lee, C.6
Lau, J.H.7
Milla, J.8
Fenner, A.9
-
29
-
-
51349168308
-
Nonlinear Thermal Stress/Strain Analysis of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps
-
Selvanayagam, C., J. H. Lau, X. Zhang, S. Seah, K. Vaidyanathan, and T. Chai, "Nonlinear Thermal Stress/Strain Analysis of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps", IEEE Proceedings of Electronic, Components & Technology Conference, Orlando, FL, May 27-30, 2008, pp. 1073-1081.
-
IEEE Proceedings of Electronic, Components & Technology Conference, Orlando, FL, May 27-30, 2008
, pp. 1073-1081
-
-
Selvanayagam, C.1
Lau, J.H.2
Zhang, X.3
Seah, S.4
Vaidyanathan, K.5
Chai, T.6
-
31
-
-
71649088048
-
Application of Piezoresistive Stress Sensors in Ultra Thin Device Handling and Characterization
-
Nov.
-
Zhang, X., A. Kumar, Q. X. Zhang, Y. Y. Ong, S. W. Ho, C. H. Khong, V. Kripesh, J. H. Lau, D.-L. Kwong, V. Sundaram, Rao R. Tummula, Georg Meyer-Berg, "Application of Piezoresistive Stress Sensors in Ultra Thin Device Handling and Characterization,"Journal of Sensors & Actuators: A. Physical, Vol. 156, Nov. 2009, pp. 2-7.
-
(2009)
Journal of Sensors & Actuators: A. Physical
, vol.156
, pp. 2-7
-
-
Zhang, X.1
Kumar, A.2
Zhang, Q.X.3
Ong, Y.Y.4
Ho, S.W.5
Khong, C.H.6
Kripesh, V.7
Lau, J.H.8
Kwong, D.-L.9
Sundaram, V.10
Tummula, R.R.11
Meyer-Berg, G.12
-
32
-
-
77953741979
-
Effects of TSV (Through Silicon Via) Interposer/Chip on the Thermal Performances of 3-D IC Packaging
-
Lau, J. H., Yue, T. G., Hoe, G. Y. Y., Zhang, X. W., Chong, C. T., Damaruganath, P., and Vaidyanathan, K. "Effects of TSV (Through Silicon Via) Interposer/Chip on the Thermal Performances of 3-D IC Packaging." ASME Paper no. IPACK2009-89380.
-
ASME Paper No. IPACK2009-89380
-
-
Lau, J.H.1
Yue, T.G.2
Hoe, G.Y.Y.3
Zhang, X.W.4
Chong, C.T.5
Damaruganath, P.6
Vaidyanathan, K.7
-
33
-
-
43249121682
-
Design and analysis of 3-D stacked optoelectronics on optical printed circuit boards
-
Also, accepted for IEEE Transactions on Advanced Packaging
-
Lau, J. H., Lim, Y., Lim, T., Tang, G., Khong, C., Zhang, X., Ramana, P., Zhang, J., Tani, C., Chandrappan, J., Chai, J., Li, J., Tangdiongga, G., and Kwong, D. "Design and analysis of 3-D stacked optoelectronics on optical printed circuit boards." In Proceedings of SPIE, Photonics Packaging, Integration, and Interconnects VIII, San Jose, CA, January 19-24, 2008, Vol. 6899, pp. 07.1-07.20. Also, accepted for IEEE Transactions on Advanced Packaging.
-
Proceedings of SPIE, Photonics Packaging, Integration, and Interconnects VIII, San Jose, CA, January 19-24, 2008
, vol.6899
-
-
Lau, J.H.1
Lim, Y.2
Lim, T.3
Tang, G.4
Khong, C.5
Zhang, X.6
Ramana, P.7
Zhang, J.8
Tani, C.9
Chandrappan, J.10
Chai, J.11
Li, J.12
Tangdiongga, G.13
Kwong, D.14
-
34
-
-
84881424273
-
State-of-the-art and Trends in Through-Silicon Via (TSV) and 3D Integrations
-
Lau, J. H., "State-of-the-art and Trends in Through-Silicon Via (TSV) and 3D Integrations, ASME Paper no. IMECE2010-37783.
-
ASME Paper No. IMECE2010-37783
-
-
Lau, J.H.1
-
35
-
-
70349666726
-
Thermal Management of 3D IC Integration with TSV (Through Silicon Via)
-
Lau, J. H., and Tang, G., "Thermal Management of 3D IC Integration with TSV (Through Silicon Via)", IEEE Proceedings of ECTC, San Diego, May 2009, pp. 635-640.
-
IEEE Proceedings of ECTC, San Diego, May 2009
, pp. 635-640
-
-
Lau, J.H.1
Tang, G.2
-
36
-
-
79251589652
-
Development of Super Thin TSV PoP
-
Carson, F., K. Ishibashi, S. Yoon, P. Marimuthu, and D. Shariff, "Development of Super Thin TSV PoP", Proceedings of IEEE CPMT Symposium Japan, August 2010, pp. 7-10.
-
Proceedings of IEEE CPMT Symposium Japan, August 2010
, pp. 7-10
-
-
Carson, F.1
Ishibashi, K.2
Yoon, S.3
Marimuthu, P.4
Shariff, D.5
-
37
-
-
79251586585
-
Thermal Stress Analysis of 3D Die Stacks with Low-Volume Interconnections
-
Kohara, S., K. Sakuma, Y. Takahashi, T. Aoki, K. Sueoka, K. Matsumoto, P. Andry, C. Tsang, E. Sprogis, J. Knickerbocker, and Y. Orii, "Thermal Stress Analysis of 3D Die Stacks with Low-Volume Interconnections", Proceedings of IEEE CPMT Symposium Japan, August 2010, pp. 165-168.
-
Proceedings of IEEE CPMT Symposium Japan, August 2010
, pp. 165-168
-
-
Kohara, S.1
Sakuma, K.2
Takahashi, Y.3
Aoki, T.4
Sueoka, K.5
Matsumoto, K.6
Andry, P.7
Tsang, C.8
Sprogis, E.9
Knickerbocker, J.10
Orii, Y.11
-
38
-
-
33845594162
-
Novel Low Cost Integration of Through Chip Interconnection and Application to CMOS Image Sensor
-
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Terabit/sec-Class Board-Level Optical Interconnects Through Polymer Waveguides Using 24-Channel Bidirectional Transceiver Modules
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Doany, F., C. Schow, B. Lee, R. Budd, C. Baks, R. Dangel, R. John, F. Libsch, and J. Kash, "Terabit/sec-Class Board-Level Optical Interconnects Through Polymer Waveguides Using 24-Channel Bidirectional Transceiver Modules", IEEE ECTC Proceedings, Orlando, Florida, June 2011, pp. 790-797.
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IEEE ECTC Proceedings, Orlando, Florida, June 2011
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111
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Design and Reliability Analysis of Pyramidal Shape 3-Layer Stacked TSV Die Package
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Che, F., T. Chai, S. Lim, R. Rajoo, and X. Zhang, "Design and Reliability Analysis of Pyramidal Shape 3-Layer Stacked TSV Die Package", IEEE ECTC Proceedings, Orlando, Florida, June 2011, pp. 1428-1435.
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IEEE ECTC Proceedings, Orlando, Florida, June 2011
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112
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Lee, J., D. Fernandez, M. Paing, Y. Yeo, and S. Gao, "Novel Chip Stacking Process for 3D Integration", IEEE ECTC Proceedings, Orlando, Florida, June 2011, pp. 1939-1943.
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IEEE ECTC Proceedings, Orlando, Florida, June 2011
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113
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Thru Silicon Via Stacking & Numerical Characterization for Multi-Die Interconnections using Full Array & Very Fine Pitch Micro C4 Bumps
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Au, K., J. Beleran, Y. Yang, Y. Zhang, S. Kriangsak, P. Wilson, Y. Drake, C. Toh, and C. Surasit, "Thru Silicon Via Stacking & Numerical Characterization for Multi-Die Interconnections using Full Array & Very Fine Pitch Micro C4 Bumps", IEEE ECTC Proceedings, Orlando, Florida, June 2011, pp. 296-303.
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IEEE ECTC Proceedings, Orlando, Florida, June 2011
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114
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Temperature-dependent Thermal Stress Determination for Through-Silicon-Vias (TSVs) by Combining Bending Beam Technique with Finite Element Analysis
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Lu, K., S. Ryu, Q. Zhao, K. Hummler, J. Im, R. Huang, and P. Ho, "Temperature-dependent Thermal Stress Determination for Through-Silicon-Vias (TSVs) by Combining Bending Beam Technique with Finite Element Analysis", IEEE ECTC Proceedings, Orlando, Florida, June 2011, pp. 1475-1480.
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IEEE ECTC Proceedings, Orlando, Florida, June 2011
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115
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A Fast Simulation Framework for Full-chip Thermo-mechanical Stress and Reliability Analysis of Through-Silicon-Via based 3D ICs
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Mitra, J., M. Jung, S. Ryu, R. Huang, S. Lim, and D. Pan, "A Fast Simulation Framework for Full-chip Thermo-mechanical Stress and Reliability Analysis of Through-Silicon-Via based 3D ICs", IEEE ECTC Proceedings, Orlando, Florida, June 2011, pp. 746-753.
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IEEE ECTC Proceedings, Orlando, Florida, June 2011
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116
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Study of the Thermo-mechanical Behavior of Glass Interposer for Flip Chip Packaging Applications
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Lin, Y., C. Hsieh, C. Yu, C. Tung, and D. Yu, "Study of the Thermo-mechanical Behavior of Glass Interposer for Flip Chip Packaging Applications", IEEE ECTC Proceedings, Orlando, Florida, June 2011, pp. 634-638.
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IEEE ECTC Proceedings, Orlando, Florida, June 2011
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117
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Electromigration Study of Micro Bumps at Si/Si Interface in 3DIC Package for 28nm Technology and Beyond
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Lin, T., R. Wang, M. Chen, C. Chiu, S. Chen, T. Yeh, L. Lin, S. Hou, J. Lin, K. Chen, S. Jeng, and D. Yu, "Electromigration Study of Micro Bumps at Si/Si Interface in 3DIC Package for 28nm Technology and Beyond", IEEE ECTC Proceedings, Orlando, Florida, June 2011, pp. 346-350.
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IEEE ECTC Proceedings, Orlando, Florida, June 2011
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118
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Comparison of the Electromigration Behaviors between Micro-bumps and C4 Solder Bumps
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Wei, C., C. Yu, C. Tung, R. Huang, C. Hsieh, C. Chiu1, H. Hsiao, Y. Chang, C. Lin, Y. Liang, C. Chen, T. Yeh, L. Lin, and D. Yu, "Comparison of the Electromigration Behaviors Between Micro-bumps and C4 Solder Bumps", IEEE ECTC Proceedings, Orlando, Florida, June 2011, pp. 706-710.
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IEEE ECTC Proceedings, Orlando, Florida, June 2011
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119
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Reliability Study of 3D-WLP Through Silicon Via with Innovative Polymer Filling Integration
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Bouchoucha, M., P. Chausse, S. Moreau, L. Chapelon, N. Sillon, O. Thomas, "Reliability Study of 3D-WLP Through Silicon Via with Innovative Polymer Filling Integration", IEEE ECTC Proceedings, Orlando, Florida, June 2011, pp. 567-572.
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IEEE ECTC Proceedings, Orlando, Florida, June 2011
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120
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Integration of Fine-Pitched Through-Silicon Vias and Integrated Passive Devices
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Shariff, D., P. Marimuthu, K. Hsiao, L. Asoy, C. Yee, A. Oo, K. Buchanan1, K. Crook, T. Wilby, and S. Burgess, "Integration of Fine-Pitched Through-Silicon Vias and Integrated Passive Devices", IEEE ECTC Proceedings, Orlando, Florida, June 2011, pp. 844-848.
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IEEE ECTC Proceedings, Orlando, Florida, June 2011
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121
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Characterization of Thermo-Mechanical Stress and Reliability Issues for Cu-Filled TSVs
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Malta, D., C. Gregory, M. Lueck, D. Temple, M. Krause, F. Altmann, M. Petzold, M. Weatherspoon, and J. Miller, "Characterization of Thermo-Mechanical Stress and Reliability Issues for Cu-Filled TSVs", IEEE ECTC Proceedings, Orlando, Florida, June 2011, pp. 1815-1821.
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IEEE ECTC Proceedings, Orlando, Florida, June 2011
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122
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Novel Anisotropic Conductive Adhesive for 3D Stacking and Lead-free PCB Packaging - A Review
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Ramkumar, S., H. Venugopalan, K. Khanna, "Novel Anisotropic Conductive Adhesive for 3D Stacking and Lead-free PCB Packaging - A Review", IEEE ECTC Proceedings, Orlando, Florida, June 2011, pp. 246-254.
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IEEE ECTC Proceedings, Orlando, Florida, June 2011
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Oprins, H., V. Cherman, B. Vandevelde, C. Torregiani, M. Stucchi, G. Van der Plas, P. Marchal, and E. Beyne, "Characterization of the Thermal Impact of Cu-Cu Bonds Achieved using TSVs on Hot Spot Dissipation in 3D Stacked ICs", IEEE ECTC Proceedings, Orlando, Florida, June 2011, pp. 861-868.
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IEEE ECTC Proceedings, Orlando, Florida, June 2011
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124
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Study on TSV with New Filling Method and Alloy for Advanced 3D-SiP
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Tsukada, A., R. Sato, S. Sekine, R. Kimura, K. Kishi, Y. Sato, Y. Iwata, and H. Murata, "Study on TSV with New Filling Method and Alloy for Advanced 3D-SiP", IEEE ECTC Proceedings, Orlando, Florida, June 2011, pp. 861-868.
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IEEE ECTC Proceedings, Orlando, Florida, June 2011
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125
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Yoon, S., K. Ishibashi, S. Dzafir, M. Prashant, P. Marimuthu, and F. Carson, "Development of Super Thin TSV PoP", IEEE ECTC Proceedings, Orlando, Florida, June 2011, pp. 274-278.
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IEEE ECTC Proceedings, Orlando, Florida, June 2011
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Evaluation of Additives and Current Mode on Copper Via Fill
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Jung, M., Y. Song, T. Yim, J. Lee, "Evaluation of Additives and Current Mode on Copper Via Fill", IEEE ECTC Proceedings, Orlando, Florida, June 2011, pp. 1908-1912.
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A Study on the 3D-TSV Interconnection using Wafer-Level Non-Conductive Adhesives (NCAs)
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Chip-to-chip Communication by Optical Routing Inside a Thin Glass Substrate
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Glass Panel Processing for Electrical and Optical Packaging
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Schröder, H., L. Brusberg, N. Arndt-Staufenbiel, J. Hofmann, S. Marx, "Glass Panel Processing for Electrical and Optical Packaging", IEEE ECTC Proceedings, Orlando, Florida, June 2011, pp. 625-633.
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IEEE ECTC Proceedings, Orlando, Florida, June 2011
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IEEE ECTC Proceedings, Orlando, Florida, June 2011
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Halder, S., A. Jourdain, M. Claes, I. Wolf, Y. Travaly, E. Beyne, B. Swinnen, V. Pepper, P. Guittet, G. Savage, and L. Markwort, "Metrology and Inspection for Process Control During Bonding and Thinning of Stacked Wafers for Manufacturing 3D SIC's", IEEE ECTC Proceedings, Orlando, Florida, June 2011, pp. 999-1002.
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High Density 20μm Pitch CuSn Microbump Process for High-End 3D Applications
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Vos, J., A. Jourdain, M. Erismis, W. Zhang, K. De Munck, A. La Manna, D. Tezcan, and P. Soussan, "High Density 20μm Pitch CuSn Microbump Process for High-End 3D Applications", IEEE ECTC Proceedings, Orlando, Florida, June 2011, pp. 27-31.
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IEEE ECTC Proceedings, Orlando, Florida, June 2011
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Wafer Level Warpage Modeling Methodology and Characterization of TSV Wafers
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Che, F., H. Li, X. Zhang, S. Gao, and K. Teo, "Wafer Level Warpage Modeling Methodology and Characterization of TSV Wafers", IEEE ECTC Proceedings, Orlando, Florida, June 2011, pp. 1196-1203.
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IEEE ECTC Proceedings, Orlando, Florida, June 2011
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Kwon, W., J. Lee, V. Lee, J. Seetoh, Y. Yeo, Y. Khoo, N. Ranganathan, K. Teo, and S. Gao, "Novel Thinning/Backside Passivation for Substrate Coupling Depression of 3D IC", IEEE ECTC Proceedings, Orlando, Florida, June 2011, pp. 1395-1399.
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IEEE ECTC Proceedings, Orlando, Florida, June 2011
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Lee, J., V. Lee, J. Seetoh, S. Thew, Y. Yeo, H. Li, K. Teo, and S. Gao, "Advanced Wafer Thinning and Handling for Through Silicon Via Technology", IEEE ECTC Proceedings, Orlando, Florida, June 2011, pp. 1852-1857.
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IEEE ECTC Proceedings, Orlando, Florida, June 2011
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