Design and fabrication of a reliability test chip for 3D-TSV

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2010, Pages 79-83

  Trigg, A D ^a   Yu, Li Hong ^a   Zhang, Xiaowu ^a   Chong, Chai Tai ^a   Kuo, Cheng Cheng ^a   Khan, Navas ^a   Daquan, Yu ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

DIE STACKING; ELECTRICAL CHARACTERIZATION; FAULT ISOLATION; MICRO-BUMPS; MOISTURE INGRESS; RELIABILITY TEST; TEST CHIPS; TEST STRUCTURE; THERMAL PERFORMANCE; THROUGH SILICON VIAS;

QUALITY ASSURANCE; THREE DIMENSIONAL;

FAILURE ANALYSIS;

EID: 77955187450     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2010.5490889     Document Type: Conference Paper

References (23)

1. Kuan H. Lu et al, "Thermo-Mechanical Reliability of 3-D ICs containing Through Silicon Vias", Proc 59th Electronic Components and Technology Conf, San Diego CA 2009, pp 630-634
2. Xi Liu et al, "Failure Mechanisms and Optimum Design for Electroplated Copper Through-Silicon Vias (TSV)", Proc 59th Electronic Components and Technology Conf, San Diego CA 2009, pp 624-629
3. Xiaowu Zhang et al, "Development of Through Silicon Via (TSV) Interposer Technology for Large Die (21x21mm) Fine-pitch Cu/low-k FCBGA Package", Proc 59th Electronic Components and Technology Conf, San Diego CA 2009, pp 305-312.
4. Aibin Yu, "Three Dimensional Interconnects with High Aspect Ratio TSVs and Fine Pitch Solder Microbumps", Proc 59th Electronic Components and Technology Conf, San Diego CA 2009, pp 350-354.
5. Srinivasa Rao Vempati et al, "Development of 3-D Silicon Die Stacked Package Using Flip Chip Technology with Micro Bump Interconnects", Proc 59th Electronic Components and Technology Conf, San Diego CA 2009, pp 980-987.
6. IME & EDB Press Release "A STAR and EDB launch 3- dimensional through-silicon via consortium to boost next generation wafer manufacturing capability for singapore semiconductor industry", Issued 8 September 2009
7. C.O. Mathuna, "Test Chips For The Evaluation Of The Performance of IC Packaging And Interconnection Technologies", IEEE CHMT IEMT Symposium, 1989 Japan, pp 286-289.
8. 8. J. N. Sweet et al, Short And Long Loop Manufacturing Feedback Using A Multi-Sensor Assembly Test Chip, M. R. Tuck, D. W. Peterson, D. W. Palm, IEEE CHMT IEMT Symposium, 1990.
9. J N Sweet, The Use of Special Purpose Assembly Test Chips for Evaluating Reliability in Packaged Devices, Wafer Level Reliability Workshop, 25-28 Oct 1992 Final Report Page(s):77-82
10. A D Trigg & A R Corless, "Thermal performance and reliability aspects of silicon hybrid multi-chip modules", Proc 40th Electronic Components and Technology Conf, Las Vegas NV 1990, pp 592 - 599
11. C O'Mathuna, "Development and Analysis of an Automated Test System for the Thermal Characterization of IC Packaging Technologies", IEEE Transactions On Components, Hybrids, And Manufacturing Technology, Vol.15, No.5, (1992), pp615-624
12. Z. Benedek et al, "A Scalable Multi-Functional Thermal Test Chip Family: Design and Evaluation", J. Electron. Packag. Vol 123, Issue 4 (2001), pp 323-330
13. Kun-Fu Tseng et al, "A Multifunctional Test Chip for Microelectronic Packaging and Its Application on RF Property Measurements", International Symposium on Electronics Materials and Packaging (EMAP2005), Tokyo, Japan, 2005, pp78-82.
14. K. Sakuma et al, "3 D chip-stacking technology with through-silicon vias and low-volume leadfree interconnections", IBM J. Res. & Dev. Vol 52 No.6 (2008) pp 611-622
15. K. Sakuma, "Characterization of Stacked Die using Die- to-Wafer Integration for High Yield and Throughput", Proc 58th Electronic Components and Technology Conf, Orlando, FL,2008, pp 18-23
16. A. P. Karmarkar, "Performance and Reliability Analysis of 3D-Integration Structures Employing Through Silicon Via (TSV)", Proc. IEEE 47th Annual International Reliability Physics Symposium, Montreal, Canada 2009 pp 682-687
17. H. H. Chang et al, "TSV Process Using Bottom-up Cu Electroplating and its Reliability Test", Proc. 2nd Electronics System-Integration Technology Conference, Greenwich, UK, 2008 pp 645-650.
18. Da-Quan Yu et al, Electromigration Study of 50 μm Pitch Micro Solder Bumps using Four-Point Kelvin Structure, Proc 59th Electronic Components and Technology Conf, San Diego CA 2009, pp 930-935
19. S.Y. Yang, et al, "Structural Reliability Assessment of Multi-Stack Package (MSP) under High Temperature Storage (HTS) testing condition", Microelectronics Reliability 46 (2006) pp 1904-1909
20. Takanori Maebashi et al, "High Density Assembly Technology using Stacking Method", Proc. IEEE 9th VLSI Packaging Workshop of Japan, Kyoto, Japan, (2008), pp149-152
21. Xiaowu Zhang et al, "A Low Stress Bond Pad Design for Low Temperature Solder Interconnections on Through Silicon Vias (TSVs)" Accepted for publication in Proc 60th Electronic Components and Technology Conf, Las Vegas NV 2009.
22. Xiaowu Zhang et al,"Application of piezoresistive stress sensors in ultra thin device handling and characterization", Sensors and Actuators A Vol 156 (2009) pp 2-7.
23. H. V. Nguyen et al, "Test Chip for Detecting Thin Film Cracking Induced by Fast Temperature Cycling and Electromigration in Multilevel Interconnect Systems", Proc 9th International Symposium on Physical and Failure Analysis (IPFA), Singapore (2002) pp 135-139.