A fast simulation framework for full-chip thermo-mechanical stress and reliability analysis of through-silicon-via based 3D ICs

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2011, Pages 746-753

  Mitra, Joydeep ^a   Jung, Moongon ^b   Ryu, Suk Kyu ^a   Huang, Rui ^a   Lim, Sung Kyu ^b   Pan, David Z ^a  

^a The University of Texas at Austin   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D ICS; CHIP LAYOUT; CHIP OPERATING TEMPERATURES; FAST SIMULATION; LINEAR SUPERPOSITIONS; LINER MATERIAL; RUNTIMES; SIMULATION TOOL; STRESS FIELD; STRESS SIMULATIONS; STRESS TENSORS; THERMO-MECHANICAL STRESS; THROUGH-SILICON-VIA;

FINITE ELEMENT METHOD; STRESSES;

RELIABILITY ANALYSIS;

EID: 79960416801     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898596     Document Type: Conference Paper

References (7)

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