Development of through silicon via (TSV) interposer technology for large die (21x21mm) fine-pitch Cu/low-k FCBGA package

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2009, Pages 305-312

  Zhang, Xiaowu ^a   Chai, T C ^a   Lau, John H ^a,f   Selvanayagam, C S ^a   Biswas, Kalyan ^b   Liu, Shiguo ^b   Pinjala, D ^a   Tang, G Y ^a   Ong, Y Y ^a   Vempati, S R ^a   Wai, Eva ^a   Li, H Y ^a   Liao, E B ^a   Ranganathan, N ^a   Kripesh, V ^a   Sun, Jiangyan ^c   Doricko, John ^d   Vath III, C J ^e  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b Ibiden Singapore Pte Ltd   (Singapore)

^c Shanghai Sinyang Semiconductor Materials Co Ltd   (China)

^d Tango Systems Inc   (United States)

^e ASM Technology Singapore Pte Ltd   (Singapore)

^f HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

ASSEMBLY PROCESS; ELECTRICAL PERFORMANCE; FABRICATION PROCESS; FCBGA PACKAGES; INTEGRITY MONITORING; MECHANICAL STRESS; METAL LAYER; MOISTURE SENSITIVITY; PB-FREE; RELIABILITY ASSESSMENTS; RELIABILITY TESTING; SILICON CHIP; SOLDER BUMP; SUBSTRATE SIZES; TEST CHIPS; THERMAL MODELING; THROUGH-SILICON-VIA; UNDERFILLS; VIA CHAIN; WIRING DENSITY;

COMPUTER SIMULATION; DIES; LEAD; METAL TESTING; RELIABILITY ANALYSIS; STRESSES; TECHNOLOGY;

SUBSTRATES;

EID: 70349658299     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2009.5074032     Document Type: Conference Paper

References (11)

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