Three dimensional chip stacking using a wafer-to-wafer integration

Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers

Volumn , Issue , 2007, Pages 81-83

  Chatterjee, Ritwik ^a   Fayolle, Murielle ^b   Leduc, Patrick ^b   Pozder, Scott ^a   Jones, Bob ^a   Acosta, Eddie ^a   Charlet, Barbara ^b   Enot, Thierry ^b   Heitzmann, Michel ^b   Zussy, Marc ^b   Roman, Antonio ^b   Louveau, Olivier ^c   Maitrejean, Sylvain ^b   Louis, Didier ^b   Kernevez, Nelly ^b   Sillon, Nicolas ^b   Passemard, Gerard ^c   Pol, Victor ^a   Mathew, Varughese ^a   Garcia, Sam ^a   Sparks, Terry ^a   Huang, Zhihong ^a   more..

^a FREESCALE SEMICONDUCTOR INC   (United States)

^b CEA LETI   (France)

^c STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BONDING; DIELECTRIC PROPERTIES; OPTICAL INTERCONNECTS; SILICON WAFERS;

DIELECTRIC WAFER BONDING; INTER-STRATA VIA (ISV); ISV CHAINS; WAFER-TO-WAFER ALIGNMENT;

INTEGRATED CIRCUIT LAYOUT;

EID: 34748923685     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iitc.2007.382355     Document Type: Conference Paper

References (6)

1. E. Beyne, Proceedings of IITC 2006, pg. 1
2. S. Pozder, et al., Proceedings of IITC 2004, pg. 102
3. K. Banerjee, et al., Proceeding of the IEEE, Vol. 89, No. 5, pg. 602, 2001
4. S. Pozder, et al., to be published, MRS 2006 Fall Proceedings
5. B. Charlet, et al., to be published, MRS 2006 Fall Proceedings
6. U. Gosele, et al. J. Vac. Sci. Tech., A17 (4), Jul/Aug 1999