3-D thin film interposer based on TGV (Through Glass Vias): An alternative to Si-interposer

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2010, Pages 66-73

  Töpper, Michael ^a   Ndip, Ivan ^a   Erxleben, Robert ^a   Brusberg, Lars ^a   Nissen, Nils ^a   Schröder, Henning ^a   Yamamoto, Hidefumi ^b   Todt, Guido ^c   Reichl, Herbert ^a  

^a FRAUNHOFER IZM   (Germany)

^b NEC SCHOTT Components Corp   (Japan)

^c SCHOTT Electronic Packaging GmbH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; ELECTRICAL ISOLATION; ELECTRO-OPTICAL; ELECTRONIC SYSTEMS; GLASS WAFER; MODELING AND SIMULATION; PRODUCTION SCALE; SI WAFER; THERMAL CYCLE; VOID-FREE; WAFER BONDING PROCESS; WAFER PROCESSING; WAFER THICKNESS;

FILM THICKNESS; GLASS; GLASS BONDING; SEMICONDUCTING SILICON COMPOUNDS; SILICON; SILICON WAFERS; THIN FILMS; THREE DIMENSIONAL; VAPOR DEPOSITION;

WAFER BONDING;

EID: 77955184310     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2010.5490887     Document Type: Conference Paper

References (18)

1. M. Töpper "Wafer Level Chip Size Packaging" in Materials for Advanced Packaging (Eds.: D. Lu, C.P. Wong), Springer Verlag 2009
2. Multichip Module Technology Handbook" edited by P. Garrou, I. Turlik, McGraw-Hill, 1998
3. F. Lärmer, A. Schilp: Verfahren zum anisotropen Ätzen von Silicium. Patent DE4241045 1992/1994
4. Brad Eaton "Deep silicon etch for TSVs with improved via profile/process control" Solid State April 2009
5. J. Leib, M. Töpper New Wafer-Level-Packaging Technology using Silicon-Via-Contacts For Optical And Other Sensor Applications, Proceedings ECTC 2004, June 2004 New Orleans, USA
6. P. Garrou "Researchers Strive for Copper TSV Reliability" Semiconductor International Dec/3/2009
7. Paul Ho "Thermo-Mechanical Reliability Challenges of 3-D Integration" 3-D Architectures for Semiconductor Integration and Packaging (Hyatt Regency San Francisco Airport Hotel, Burlingame, California Dec. 2009)
8. Phillip Garrou "Qualcomm's Nowak: 3-D Faces Cost Issues" Semiconductor International, October/6/2009
9. Yannou, J.-M. Neuilly, F. Moreno, J.-A. Pommier, M. Bellenger, S. Biermans, P "NXP System-in-Package vision and latest 3D technology developments" ADVANCING MICROELECTRONICS, VOL 34; NUMB 6, pages 16-21 2007
10. Brusberg, L., Schröder, H., Erxleben, R., Ndip, I., Töpper, M., Nissen, N., Reichl, H., "Glass Carrier Based Packaging Approach Demonstrated on a Parallel Optoelectronic Transceiver Module for PCB Assembling", Proc. 60th Electronic Components and Technology Conference, Las Vegas, NY, USA (2010)
11. Schott AG, Advanced Materials: Glass Specifications (www.schott.com)
12. H. Schröder, L. Brusberg, R. Erxleben, I. Ndip, M. Töpper, N. F. Nissen, H. Reichl glassPack - A 3D Glass Based Interposer Concept for SiP with Integrated Optical Interconnects Proc. 60th Electronic Components and Technology Conference, Las Vegas, NY, USA (2010)
13. www.invenios.com
14. J.H. Park et al. "Deep dry etching of borosilicate glass using SF6 and SF6/Ar inductively coupled plasmas" Microelectronic Engineering Volume82, Issue 2, October 2005, Pages 119-128
15. Xiaoyun Cui et al, Proc. Of. EPTC 2008
16. Carsten Wesselkamp "Advanced Substrates for MEMS packaging and Conductive Via Wafers" MicroMachine 2008, Tokyo 2008
17. http://www.schott.com/epackaging/english/auto/others/hermes.html
18. J. Leib, O. Gyenge, U. Hansen, S. Maus, M. Töpper, K. Zoschke "Thin Hermetic Passivation of semiconductors using low temperature Borosilicate Glass - Benchmark of a new wafer-level packaging technology" Proceedings ECTC 2009, San Diego