3D chip stacking & reliability using TSV-micro C4 solder interconnection

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2010, Pages 1376-1384

  Au, K Y ^a   Kriangsak, S L ^a   Zhang, X R ^a   Zhu, W H ^a   Toh, C H ^a  

^a United Test and Assembly Center Ltd UTAC   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

BOND PAD; CAP THICKNESS; CHIP STACKING; CLEANING METHODS; DIE STACKING; ELECTRONIC DEVICE; FINITE ELEMENT SIMULATIONS; FLOW PROCESS; FORCE FLOW; IN-LINE; LOW COSTS; LOW CTE; METALLIZATIONS; MICRO GAPS; ORGANIC SUBSTRATE; RELIABILITY PERFORMANCE; SILICON DIE; SOLDER BUMP; SOLDER INTERCONNECTIONS; SPRAY SYSTEMS; STACKED DIE; THERMAL CYCLE; THROUGH-SILICON-VIA; WARPAGES;

DIES;

EID: 77955208213     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2010.5490636     Document Type: Conference Paper

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