Solder/adhesive bonding using simple planarization technique for 3D integration

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2011, Pages 1147-1152

  Nimura, Masatsugu ^a   Mizuno, Jun ^a   Sakuma, Katsuyuki ^b   Shoji, Shuichi ^a  

^a WASEDA UNIVERSITY   (Japan)

^b IBM RESEARCH TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; AU BUMP; BONDING METHODS; CHIP BONDING; CMP PROCESS; CROSS-SECTIONAL SEM IMAGE; HYBRID BONDING; ONE STEP; PLANARIZATION PROCESS; PLANARIZATION TECHNIQUE; RELEASE AGENT; RESIDUAL LAYERS; SI SUBSTRATES; SMALL GAPS; THREE DIMENSIONAL (3D) INTEGRATION; UNDERFILL RESINS; WAFER-LEVEL FABRICATION;

CHEMICAL MECHANICAL POLISHING; SILICON WAFERS; THREE DIMENSIONAL;

WAFER BONDING;

EID: 79960423083     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898655     Document Type: Conference Paper

References (21)

1. Katsuyuki Sakuma et al., "3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections", IBM Journal of Research and Development, Vol. 52, No. 6 (2008), pp. 611-622.
2. M. Koyanagi et al., "Future System-on-Silicon LSI Chips", IEEE Micro, Vol. 18, No. 4 (1998), pp. 17-21.
3. K. M. Chen, "Comparing the Impacts of the Capillary and the Mooded Underfill Process on the Reliability of the Flip-Chip BGA", IEEE Transactions on components and packaging technologies, Vol. 31, No. 3 (2008), pp. 586-591.
4. Kang Wook et al., "Development of Three-Dimensional Integration Technology for Highly Parallel Image-Processing Chip", Japanese Journal of Applied Physics, Vol. 39, No. 4 (2000), pp. 2473-2477.
5. th Electronic Components and Technology Conference (ECTC), 2002, pp. 1454-1459.
6. th Electronic Components and Technology Conference (ECTC), 1995, pp. 1240-1243.
7. K. M. Chen, "Comparing the Impacts of the Capillary and the Mooded Underfill Process on the Reliability of the Flip-Chip BGA", IEEE Transactions on components and packaging technologies, Vol. 31, No. 3 (2008), pp. 586-591.
8. th Electronic Components and Technology Conference (ECTC), 2001, pp. 310-316.
9. th Electronic Components and Technology Conference (ECTC), 2001, pp. 1502-1505.
10. Sangil Lee et al., "Void Formation Study of Flip Chip in Pachage Using No-Flow Underfill", IEEE Transactions on electronics packaging manufacturing, Vol. 31, No. 4 (2008), pp. 297-305.
11. th Electronic Components and Technology Conference (ECTC), 1998, pp. 1253-1259.
12. th Electronic Components and Technology Conference (ECTC), 2005, pp. 331-336.
13. th Electronic Components and Technology Conference (ECTC), 2008, pp. 871-878.
14. Jian-Qiang et al., "3D Integration Using Adhesive, Metal, and Metal/Adhesive as Wafer Bonding Interfaces", Proceedings of the Materials Research Society (MRS), Vol. 1112, 2009, pp. 69-80.
15. F. Liu et al., "A 300-mm Wafer-Level Three-Dimensional Integration Scheme Using Tungsten Through-Silicon Via and Hybrid Cu-Adhesive Bonding", Proceedings of the International Electron Device meeting (IEDM), 2008, pp. 1-4.
16. R. R. Yu et al., "Reliability of a 300-mm-compatible 3DI Technology Based on Hybrid Cu-adhesive Wafer Bonding", Proceedings of the Symposium on VLSI Technology, 2009, pp. 170-171.
17. rd Electronic System-Integration Technology Conference (ESTC), 2010, pp. 1-5.
18. th of the Electronics Packaging Technology Conference (EPTC), 2009, pp. 267-271.
19. th Electronic Components and Technology Conference (ECTC), 2002, pp. 1380-1384.
20. th Electronic Components and Technology Conference (ECTC), 2000, pp. 101-106.
21. th of Electronics Packaging Technology Conference (EPTC), 2003, pp. 194-198.