Integrated process for defect-free copper plating and chemical-mechanical polishing of through-silicon vias for 3D interconnects

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2010, Pages 1769-1775

  Malta, Dean ^a   Gregory, Christopher ^a   Temple, Dorota ^a   Knutson, Trevor ^b   Wang, Chen ^c   Richardson, Thomas ^c   Zhang, Yun ^c   Rhoades, Robert ^d  

^a RTI INTERNATIONAL   (United States)

^b Egypt   (United States)

^c Enthone Inc   (United States)

^d Entrepix Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTERCONNECTS; 3D PACKAGING; BOTTOM-UP FILLING; CHEMICAL-MECHANICAL POLISHING PROCESS; CMP PROCESS; COPPER INTERCONNECTS; CU ELECTROPLATING; CU FILMS; DEFECT-FREE; INTEGRATED PROCESS; LARGE DIAMETER; METALLIZATIONS; NONUNIFORMITY; PLATING PROCESS; POLISHING TIME; THREE DIMENSIONAL (3D) INTEGRATION; THROUGH SILICON VIAS; VOID-FREE; WAFER LEVEL PACKAGING;

ASPECT RATIO; CHEMICAL MECHANICAL POLISHING; COPPER; COPPER PLATING; DEFECTS; POLISHING; SILICON WAFERS; TECHNOLOGY; THREE DIMENSIONAL;

CHEMICAL POLISHING;

EID: 77955220951     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2010.5490731     Document Type: Conference Paper

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