A silicon interposer BGA package with Cu-filled TSV and multi-layer Cu-plating interconnect

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2008, Pages 571-576

  Kumagai, Kouichi ^a   Yoneda, Yuko ^a   Izumino, Hitoshi ^a   Shimojo, Hiroko ^a   Sunohara, Masahiro ^b   Kurihara, Takashi ^b   Higashi, Mitsutoshi ^b   Mabuchi, Yoshihiro ^a  

^a System Fabrication Technologies Inc   (Japan)

^b SHINKO ELECTRIC INDUSTRIES CO LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BATCH DATA PROCESSING; COMPUTER NETWORKS; COPPER; ELECTRIC CURRENTS; PLATING; SILICON; TECHNOLOGY;

BGA PACKAGES; ELECTRONIC COMPONENTS; MULTI LAYERING;

SEMICONDUCTING SILICON COMPOUNDS;

EID: 51349119303     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2008.4550030     Document Type: Conference Paper

References (3)

1. J. U. Knickerbocker et al, "Three Dimensional Silicon Integration Using Fine Pitch Interconnection, Silicon Processing and Silicon Carrier Packaging Technology," Proc. of 2005 CICC, pp.659-662, Sep. 2005
2. K. Kumagai et al, "System-in-Silicon Architecture and its Application to H.264/AVC Motion Estimation for 1080HDTV," ISSCC Dig. Tech. Papers, pp.430-431, Feb. 2006
3. M.Akazawa et al, "High density packaging technology on silicon substrate," in Proc. 53th ECTC, May 2003, pp.647-651.