Zero-level packaging for (RF-)MEMS implementing TSVs and metal bonding

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2011, Pages 1588-1595

  Pham, Nga P ^a   Cherman, Vladimir ^a   Vandevelde, Bart ^a   Limaye, Paresh ^a   Tutunjyan, Nina ^a   Jansen, Roelof ^a   Van Hoovels, Nele ^a   Tezcan, Deniz S ^a   Soussan, Philippe ^a   Beyne, Eric ^a   Tilmans, Harrie A C ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; CAPPING SUBSTRATES; CRITICAL STRESS; EXTERNAL PRESSURES; FABRICATION PROCESS; METAL BONDING; MICRO-BUMPS; PACKAGING TECHNOLOGIES; THERMO-MECHANICAL; VERTICAL FEEDTHROUGHS; ZERO-LEVEL PACKAGING;

CHIP SCALE PACKAGES; HERMETIC SEALS; SILICON WAFERS; STRESSES;

PACKAGING;

EID: 79960388942     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898723     Document Type: Conference Paper

References (17)

1. Tilmans H. A. C., Jourdain A. and De Moor P., "Packaging", Chapter 9 in "Advanced RF MEMS", S. Lucyszyn (ed.), Cambridge Press, 2010.
2. Henderson R. M., Herrick K. J., Weller T. M., Robertson S. V., Kihm R. T. and Katehi L. P. B., "Three-dimonsional high-frequency distribution networks-Part II: Packaging and integration", IEEE Trans. on Microwave Theory and Techniques, 48, no. 10, Oct. 2000 pp. 1643-1651.
3. Jourdain A, Rottenberg X, Carchon G. and Tilmans H. A. C, "Optimization of 0-level packaging for RF-MEMS devices", proc. Transducers'03, Boston, USA, June 8-12, 2003, pp. 1915-1918
4. Jourdain A., Brebels S., De Raedt W., Tilmans H. A. C., "Influence of 0-level packaging on the microwave performance of RF-MEMS devices", Proc. European Microwave Conference EuMC 2001, pp. 403-406.
5. Min B. W, Entesari K, Rebeiz G., "DC-50GHz low-loss wafer-scale package for RF-MEMS", Proc. European Microwave Conference EuMC 2004, pp. 1289-1291.
6. Gannudi H. El., Farinelli P., I. Pieper, Chiuppesi E., Sorrentino R., "Design and Manufacturing of Wideband Buried RF Feedthroughs for Wafer-Level RF MEMS Package", Proc. of the 5th European Microwave Integrated Circuits Conference (EuMIC2010), 27-28 September 2010, Paris (France), pp. 321-324.
7. Fujii M., Kimura I., Satoh T. and Imanaka K., "RF MEMS switch with wafer level package utilizing frit glass bonding", proc. 32nd European Microwave Conference EUMC2002, Milan, Italy, 23-27 September 2002 (vol. 1), pp. 279-281
8. Margomenos A., Peroulis D., Herrick K. J. and Katehi L. P. B., "Silicon micromachined packages for RF MEMS switches", proc. 31st European Microwave Conference EUMC2001, London, UK, September 25-27, 2001, pp. 271-274(vol. 1), 2001.
9. Hsu Li-Han, Wu Wei-Cheng, Chang Edward Yi, Zirath Herbert, Wu Yun-Chi, Wang Chin-Te, and Lee Ching-Ting, "Design and fabrication of 0/1-level RF-via interconnect for RF-MEMS packaging applications", IEEE Trans. on Adv. Packaging, vol 33 (1), Feb. 2010, pp. 30-36.
10. Ferrandon C., Greco F., Lagoutte E., Descours P., Enyedy G., Pellat M., Gillot C., Rey P., Mercier D., Cueff M., Baillin X., Perruchot F., Sillon N., Liu L. J., Pacheco S., Miller M., "Hermetic wafer-level packaging development for RF MEMS switch", proc. Electronics System Integration Technology Conference ESTC2010, September 13-16, 2010, Berlin (Germany).
11. Tong D. W., John L. Benjamin and W. R. van Dell, "Interface effects of SIPOS passivation", IEEE Trans. on El. Dev., Vol. ED-33, No. 6, June 1986, pp. 779-787.
12. Detcheverry C., van Noort W. D., Havens R. J., "New lowcost thermally stable process to reduce silicon substrate losses: A way to extreme frequencies for high volume Si technologies", proc. IEDM2004, pp.
13. Majeed, B.; Van Cauwenberghe, M.; Sabuncuoglu Tezcan D. and Soussan, P., "Failure analysis and process improvement for through silicon via interconnects", Proc MRS Symposium: Materials, Processes and Reliability for Advanced Interconnects for Micro-and Nanoelectronics, San Francisco, CA, USA, April 2009, vol. 1156, pp. 1156-D08-04
14. Labie R., "Mechanical and physical behaviour of intermetallics in leadfree flip chip interconnects", Ph. D dissertation, K. U. Leuven (Belgium), 2007.
15. th Electronics Packaging Technology Conf. (EPTC2010), Singapore, Dec. 2010, pp. 1-6.
16. Rong B., Burghartz J. N., Nanver L. K., Rejaei B., and van der Zwan M., "Surface-passivated high-resistivity silicon substrates for RFICs", IEEE El. Dev. Lett., vol. 25 (4), April 2004, pp. 176-178.
17. Vandevelde, B.; Jansen, R.; Bouwstra, S.; N. Pham, N.; Majeed, B.; Limaye, P.; Beyne, E. and Tilmans, H. A. C., "Thermo-mechanical design of a generic 0-level MEMS package using chip cappping and Through Silicon Vias", proc. 11th International Conference on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics - EuroSimE. 2010, 26-28 April 2010; Bordeaux, France.