SCOPUS 정보 검색 플랫폼

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2011, Pages 553-559

Low-profile 3D silicon-on-silicon multi-chip assembly

(5) Andry, P a Dang, B a Knickerbocker, J a Tamura, K b Taneichi, N b

a IBM T J WATSON RESEARCH CENTER (United States)

b TOKYO OHKA KOGYO CO LTD (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BATCH SIZES; CU WIRING; ELECTRICAL EFFECTS; ELECTRICAL MEASUREMENT; FOUR-POINT; LEAD FREE SOLDERS; LEAD-FREE; LOW PROFILE; MULTI-CHIP; RESISTANCE SHIFTS; SILICON SUBSTRATES; SILICON-ON-SILICON; SOLDER INTERCONNECTS;

SEMICONDUCTING SILICON COMPOUNDS; SILICON WAFERS; TIN; TUNGSTEN;

THREE DIMENSIONAL;

EID: 79960408075 PISSN: 05695503 EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/ECTC.2011.5898566 Document Type: Conference Paper

Times cited : (7)

References (8)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.