TSV based silicon interposer technology for wafer level fabrication of 3D SiP modules

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2011, Pages 836-843

  Zoschke, K ^a   Wolf, J ^a   Lopper, C ^a   Kuna, I ^a   Jurgensen, N ^a   Glaw, V ^a   Samulewicz, K ^a   Roder, J ^b   Wilke, M ^a   Wunsch, O ^b   Klein, M ^a   Suchodoletz, M V ^a   Oppermann, H ^a   Braun, T ^a   Wieland, R ^c   Ehrmann, O ^a  

^a FRAUNHOFER IZM   (Germany)

^b TECHNISCHE UNIVERSITÄT BERLIN   (Germany)

^c Fraunhofer Institut fur Festkorpertechnologie   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

3D ARCHITECTURES; ELECTRICAL RESISTANCES; FINE PITCH; FORMATION PROCESS; HIGH ASPECT RATIO; HIGH DENSITY; HIGH DENSITY WIRING; KEY COMPONENT; LATERAL DIMENSION; LOW LOSS; PACKAGE LEVELS; PARASITIC EFFECT; PERFORMANCE SIGNALS; PRODUCTION EQUIPMENTS; THROUGH SILICON VIAS; WAFER LEVEL; WAFER LEVEL PROCESSING; WAFER TO WAFER BONDING; WAFER-LEVEL FABRICATION;

ASPECT RATIO; BONDING; CONDUCTIVE MATERIALS; COPPER; ELECTRONICS PACKAGING; SEMICONDUCTING SILICON COMPOUNDS; SILICON WAFERS; THREE DIMENSIONAL;

WAFER BONDING;

EID: 79960420838     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898608     Document Type: Conference Paper

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