Integration of TSVs, wafer thinning and backside passivation on full 300mm CMOS wafers for 3D applications

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2011, Pages 1122-1125

  Jourdain, Anne ^a   Buisson, Thibault ^a   Phommahaxay, Alain ^a   Redolfi, Augusto ^a   Thangaraju, Sarasvathi ^a   Travaly, Youssef ^a   Beyne, Eric ^a   Swinnen, Bart ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTERCONNECTS; 3D APPLICATION; 3D TECHNOLOGY; CMOS WAFERS; PRODUCTION LINE; THIN WAFERS; THROUGH SILICON VIAS; WAFER THINNING;

PASSIVATION; SEMICONDUCTING SILICON COMPOUNDS; TECHNOLOGY; THREE DIMENSIONAL;

SILICON WAFERS;

EID: 79960409837     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898650     Document Type: Conference Paper

References (4)

1. E. Beyne et al., "Through-Si-Via Technology Solutions for 3D System Integration", Solid State Devices and Materials Conference, October 2009, Sendai, Japan.
2. J. Van Olmen et al., "3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer Bonding with copper Through Silicon Vias (TSV)", Proc. IEEE 3DIC 2009, September 2009, San Francisco.
3. A. Jourdain et al. "300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications", Proc. 3DIC 2010, November 2010, Munich.
4. L. Zhao et al., "A New Perspective of Barrier Material Evaluation and Process Optimization", Proc. IEEE International Interconnect Technology Conference, 2009.