|
Volumn , Issue , 2008, Pages 314-318
|
A novel, wafer-level stacking method for low-chip yield and non-uniform, chip-size wafers for MEMS and 3D SIP applications
|
Author keywords
[No Author keywords available]
|
Indexed keywords
APPLICATION SPECIFIC INTEGRATED CIRCUITS;
CMOS INTEGRATED CIRCUITS;
COMPOSITE MICROMECHANICS;
COMPUTER NETWORKS;
ELECTRIC POWER SUPPLIES TO APPARATUS;
ELECTRONIC EQUIPMENT MANUFACTURE;
MEMS;
MICROELECTROMECHANICAL DEVICES;
SEMICONDUCTING SILICON COMPOUNDS;
SILICON;
SILICON WAFERS;
WAFER BONDING;
CHIP SIZES;
MEMS DEVICES;
NON UNIFORM;
ELECTRONICS PACKAGING;
|
EID: 51449095637
PISSN: 05695503
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/ECTC.2008.4549988 Document Type: Conference Paper |
Times cited : (24)
|
References (6)
|