Through-package-via formation and metallization of glass interposers

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2010, Pages 557-563

  Sukumaran, Vijay ^a   Chen, Qiao ^a   Liu, Fuhan ^a   Kumbhat, Nitesh ^a   Bandyopadhyay, Tapobrata ^a   Chan, Hunter ^a   Min, Sunghwan ^a   Nopper, Christian ^b   Sundaram, Venky ^a   Tummala, Rao ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRICAL INSULATION; ELECTRICAL PROPERTY; FINE PITCH; LOW COSTS; METALLIZATIONS; ORGANIC MATERIALS; ORGANIC SUBSTRATE; SILICON-BASED; VIA-WALL;

DIMENSIONAL STABILITY; ELECTRIC PROPERTIES; GLASS; METALLIZING; SILICON WAFERS; TECHNOLOGY;

SEMICONDUCTING SILICON COMPOUNDS;

EID: 77955193795     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2010.5490913     Document Type: Conference Paper

References (15)

1. B. Garben, et al., "Organic Chip Packaging Technology For High Speed Processor Applications," in Signal Propagation on Interconnects, 6th IEEE Workshop on. Proceedings, 2002, pp. 119-122.
2. E. Klink, et al., "Evolution of organic chip packaging technology for high speed applications," Advanced Packaging, IEEE Transactions on, vol.27, pp. 4-9, 2004.
3. R. R. Tummala, et al., "Fundamental Limits of Organic Packages and Boards and the Need for Novel Ceramic Boards for Next Generation Electronic Packaging," Journal of Electroceramics, vol.13, pp. 417-422, 2004.
4. R. R. Tummala, et al., "Trend from ICs to 3D ICs to 3D systems," in Custom Integrated Circuits Conference, 2009. CICC '09. IEEE, 2009, pp. 439-444.
5. M. Sunohara, et al., "Silicon interposer with TSVs (Through Silicon Vias) and fine multilayer wiring," in Electronic Components and Technology Conference, 2008. ECTC 2008. 58th, 2008, pp. 847-852.
6. X. Cui, et al., "Glass as a substrate for high density electrical interconnect," in 10th Electronics Packaging Technology Conference, EPTC 2008, December 9, 2008 - December 12, 2008, Singapore, Singapore, 2008, pp. 12-17.
7. D. A. Hutt, et al., "Challenges in the manufacture of glass substrates for electrical and optical interconnect," in ESTC 2006-1st Electronics Systemintegration Technology Conference, September 5, 2006-September 7, 2006, Dresden, Saxony, Germany, 2007, pp. 1279-1285.
8. T. Bandyopadhyay, et al., "Electrical modeling of Through Silicon and Package Vias," in 3D System Integration, 2009. 3DIC 2009. IEEE International Conference on, 2009, pp. 1-8.
9. A. Goyal, et al., "High speed anisotropic etching of Pyrex® for microsystems applications," Journal of Non-Crystalline Solids, vol.352, pp. 657-663, 2006.
10. T. Ichiki, et al., "Deep dry etching of borosilicate glass using fluorine-based high-density plasmas for microelectromechanical system fabrication," Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, vol.21, pp. 2188-2192, 2003.
11. K. Kolari, "Deep plasma etching of glass with a silicon shadow mask," Sensors and Actuators A: Physical, vol.141, pp. 677-684, 2008.
12. D. Bhatt, et al., "Process Optimisation and Characterization of Excimer Laser Drilling of Microvias in Glass," in Electronics Packaging Technology Conference, 2007. EPTC 2007. 9th, 2007, pp. 196-201.
13. C. Xiaoyun, et al., "Copper Deposition and Patterning for Glass Substrate Manufacture," in Electronics Packaging Technology Conference, 2007. EPTC 2007. 9th, 2007, pp. 37-42.
14. J. Xu, et al., "Selective metallization on insulator surfaces with femtosecond laser pulses," Optics Express, vol.15, pp. 12743-12748, 2007.
15. V. Sridharan, et al., "Design and Fabrication of Bandpass Filters in Glass Interposer with Through-Package-Vias (TPV)," in Electronic Components and Technology Conference, 2010. ECTC 2010. 60th, 2010.