Effective thermal via and decoupling capacitor insertion for 3D system-on-package

Proceedings - Electronic Components and Technology Conference

Volumn 2006, Issue , 2006, Pages 1795-1801

  Wong, Eric ^a   Minz, Jacob ^a   Lim, Sung Kyu ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITORS; DENSITY (SPECIFIC GRAVITY); MAGNETIC COUPLINGS; PROBLEM SOLVING; SPURIOUS SIGNAL NOISE;

3D SYSTEM-ON-PACKAGE (SOP); DECOUPLING CAPACITORS; POWER SUPPLY NOISE COUPLING; THERMAL VIAS;

ELECTRONICS PACKAGING;

EID: 33845581077     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2006.1645903     Document Type: Conference Paper

References (10)

1. G. Forsythe and R. Leibler, "Matrix inversion by a monte carlo method," Mathematical Tables and Other Aids to Computation, 1950.
2. W. Wasow, "A note on the inversion of matrices by random walks," Mathematical Tables and Other Aids to Computation, 1952.
3. P. Doyle and J. Snell, "Random walks and electric networks," Mathematical Association of America, 1984.
4. Q. H. Qian, S. Nassif, and S. Sapatnekar, "Random walks in a supply network," in Proc. ACM Design Automation Conf., 2003.
5. Q. H. Qian and S. Sapatnekar, "Hierarchical random-walk algorithms for power grid analysis," in Proc. Asia and South Pacific Design Automation Conf., 2004.
6. X. Tang, R. Tian, and D. F. Wang, "Fast evaluation of sequence pair in block placement by longest common subsequence computation," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 2001.
7. S. Zhao, C. Koh, and K. Roy, "Decoupling capacitance allocation and its application to power supply noise aware floorplanning," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 81-92, 2002.
8. E. Wang, J. Minz, and S. K. Lim, "Power Noise-aware 3D Floorplanning for System-On-Package," in Proc. IEEE Electrical Performance of Electronic Packaging, 2005.
9. Y. Tsai, A. Ankadi, N. Vijaykrishnan, M. Irwin, and T. Theocharides, "ChipPower: An Architecture-Level Leakage Simulator," in Proc. IEEE Int. SOC Conf., 2004.
10. GSRC, http://www.cse.ucsc.edu/research/surf/GSRC/GSRCbench.html.