Thermal stress induced delamination of through silicon vias in 3-D interconnects

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2010, Pages 40-45

  Lu, Kuan H ^a   Ryu, Suk Kyu ^a   Zhao, Qiu ^a   Zhang, Xuefeng ^a   Im, Jay ^a   Huang, Rui ^a   Ho, Paul S ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTERCONNECTS; ANALYTICAL SOLUTIONS; CRACK DRIVING FORCE; DRIVING FORCES; FINITE ELEMENT ANALYSIS; FRACTURE MECHANISMS; INTERFACIAL DELAMINATION; LONG CRACKS; METAL PAD; METALLIZATIONS; MODELING RESULTS; STEADY STATE; THERMAL MISMATCH; THROUGH SILICON VIAS; THROUGH-SILICON-VIA;

DELAMINATION; FINITE ELEMENT METHOD; STEEL SHEET; STRUCTURAL DESIGN; THERMAL CYCLING; THERMAL STRESS; THERMOELASTICITY; TUNGSTEN;

CRACKS;

EID: 77955187970     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2010.5490883     Document Type: Conference Paper

References (6)

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4. Thompson, S. et al, "Uniaxial-Process-Induced Strained-Si: Extending the CMOS Roadmap," IEEE Trans. Electron Devices, Vol.53, No.5, May 2006.
5. th Electronic Components and Technology Conf, San Diego, CA, May 2009, pp. 624-629.
6. Ryu, S.-K. et al, "The Effect of Near-Surface Thermal Stresses on Reliability of Through-Silicon-Vias (TSVs) in 3-D Interconnects," in preparation.