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Volumn , Issue , 2011, Pages 999-1002

Metrology and inspection for process control during bonding and thinning of stacked wafers for manufacturing 3D SIC's

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; CHIP STRUCTURES; DEPTH VARIATION; DEVICE WAFERS; GLUE LAYERS; IC MANUFACTURING TECHNOLOGIES; IC TECHNOLOGY; IN-LINE METROLOGY; MAINSTREAM PROCESS; SINGLE CHIPS; VERTICAL DIRECTION; WAFER METROLOGY;

EID: 79960415928     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898631     Document Type: Conference Paper
Times cited : (14)

References (5)
  • 1
    • 79960421634 scopus 로고    scopus 로고
    • Proc. of the 1st, 2nd and 3rd conf. on "3D architectures for semiconductor integration and packaging"
    • Burlingame, California, April 13-15, Burlingame, California, October 31 - November 2, 2006
    • Proc. of the 1st, 2nd and 3rd conf. on "3D Architectures for Semiconductor Integration and packaging", RTI international, Burlingame, California, April 13-15, 2004; Tempe, Arizona, June 13-15, 2005; Burlingame, California, October 31 - November 2, 2006
    • (2004) RTI International
  • 2
    • 2442641371 scopus 로고    scopus 로고
    • 3D Interconnection and packaging: Impending reality or still a dream?
    • ISSCC2004, 15-19 February, San Francisco, CA, USA, IEEE, 2004
    • Beyne, E. "3D Interconnection and packaging: impending reality or still a dream? Proceedings of the IEEE International Solid-State Circuits Conference, ISSCC2004, 15-19 February 2004; San Francisco, CA, USA, IEEE, 2004, pp. 138-145
    • (2004) Proceedings of the IEEE International Solid-state Circuits Conference , pp. 138-145
    • Beyne, E.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.