Development of 3-D silicon die stacked package using flip chip technology with micro bump Interconnects

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2009, Pages 980-987

  Vempati, Srinivasa Rao ^a   Su, Nandar ^a   Khong, Chee Houe ^a   Lim, Ying Ying ^a   Vaidyanathan, Kripesh ^a   Lau, John H ^a,d   Liew, B P ^b   Au, K Y ^b   Tanary, Susanto ^b   Fenner, Andy ^c   Erich, Robert ^c   Milla, Juan ^c  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b UTAC   (Singapore)

^c MMC   (United States)

^d HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

BACKGRINDING; CHIP-LEVEL; DIFFERENT SIZES; FLIP CHIP BONDING; FLIP CHIP TECHNOLOGIES; HIGH DENSITY; HIGH TEMPERATURE STORAGE TEST; HIGH-ACCELERATED STRESS TESTS; LEVEL-1; MECHANICAL SIMULATIONS; MICRO-BUMPS; MOISTURE SENSITIVITY; PACKAGE DENSITY; PACKAGE LEVELS; PACKAGE RELIABILITY; PARAMETRIC STUDY; PB-FREE; PRODUCT MINIATURIZATION; RELIABILITY TEST; SILICON DIE; SNPB SOLDER; STACKED MODULES; STACKED PACKAGE; SUBSTRATE MATERIAL; TEMPERATURE CYCLE TEST; TEST CHIPS; TEST STRUCTURE; THREE DIMENSIONAL PACKAGING; THREE-DIMENSIONAL (3D) PACKAGING; UNDERFILL MATERIALS; UNDERFILL PROCESS; WARPAGES;

COMPUTER OPERATING PROCEDURES; DIES; ELECTRIC BATTERIES; ELECTRONIC EQUIPMENT MANUFACTURE; FLIP CHIP DEVICES; HIGH TEMPERATURE SUPERCONDUCTORS; MEDICAL APPLICATIONS; MINIATURE INSTRUMENTS; MONOLITHIC MICROWAVE INTEGRATED CIRCUITS; RELIABILITY ANALYSIS; SILICON WAFERS; SOLDERING ALLOYS; STRESS ANALYSIS; TECHNOLOGY; TESTING; THREE DIMENSIONAL; WAFER BONDING;

CHIP SCALE PACKAGES;

EID: 70349670743     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2009.5074132     Document Type: Conference Paper

References (10)

1. E Jan Vardaman and Linda Matthew "New Developments in Stacked Die CSPs" in Proc, HDP, pp.29-30, 2004.
2. Boon Howe Oh et.al, "Challenges in Stacked CSP Packaging Technology" " in Proc, EMAP Conf, pp.1-4, 2006.
3. Baik-Woo Lee et.al, "New 3-D Chip Stacking Architectures by Wire-on-Bump and Bump-on-Flex" IEEE Transactions on Advance Packaging, Vol.31, No.2, pp.367-376, 2008.
4. http://www.technicalmaterials.umicore.com/en/bt/datenblaetter/ show-BrazeTec-4.pdf.
5. ww.amtest.net/pdf/materials/qualitek/ Qualitek%20Solder%20Paste%20865A%20TDS.pdf.
6. M. G. Pecht, et al, "Electronic Packaging Materials and Their Properties", CRC Press LLC, Boca Raton, 1998.
7. Z. Mei, J.W. Morris, "Characterization of Eutectic Sn-Bi Solder Joints", Journal of Electronic Materials, vol 21, no. 6, 1992.
8. H. Mavoori, et al, "Creep, Stress Relaxation, and Plastic Deformation in Sn-Ag and Sn Zn Eutectic Solders", Journal of Electronic Materials, vol 26, no. 7, 1997.
9. Z.N. Cheng, et al. "Viscoplastic Anand Model for solder alloys and its application", Soldering and Surface Mount Technology, 12/2 [2000] 31-36.
10. http://www.jedec.org/Home/about-jedec.cfm.