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Volumn 2006, Issue , 2006, Pages 1367-1374

Novel low cost integration of through chip interconnection and application to CMOS image sensor

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Indexed keywords


EID: 33845594162     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2006.1645835     Document Type: Conference Paper
Times cited : (38)

References (9)
  • 1
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    • Aug.
    • L.W. Schaper, et al., "Architectural Implications and Process Development of 3-D VLSI Z-Axis Interconnects Using Through Silicon Vias," IEEE Trans. Advanced Packaging, Vol. 28, No. 3, pp. 356-366 (Aug. 2005).
    • (2005) IEEE Trans. Advanced Packaging , vol.28 , Issue.3 , pp. 356-366
    • Schaper, L.W.1
  • 2
    • 0041610704 scopus 로고
    • Three-dimensional Integration Technology Based on Wafer Bonding Technique Using Micro-bumps
    • Ext. Abstr. Osaka, Japan, August
    • T. Matsumoto, T. et al., "Three-Dimensional Integration Technology Based on Wafer Bonding Technique Using Micro-Bumps," Ext. Abstr. 1995 Int. Conf. Solid State Devices Mater., Osaka, Japan, August 1995, pp. 1073-1074.
    • (1995) 1995 Int. Conf. Solid State Devices Mater. , pp. 1073-1074
    • Matsumoto, T.1
  • 3
    • 0031270573 scopus 로고    scopus 로고
    • Three dimensional metallization for vertically integrated circuits
    • P. Ramm, et al., "Three dimensional metallization for vertically integrated circuits," Microelectron. Eng., Vol. 37/38 (1997), pp. 39-47.
    • (1997) Microelectron. Eng. , vol.37-38 , pp. 39-47
    • Ramm, P.1
  • 5
    • 0043113510 scopus 로고    scopus 로고
    • 128Mbit NAND flash memory by chip-on-chip technology with cu through plug
    • Tokyo, Japan, April
    • K. Sasaki, et al., "128Mbit NAND Flash Memory by Chip-on-Chip Technology with Cu Through Plug," 2001 Int. Conf. Electron. Packaging Proc., Tokyo, Japan, April 2001, pp. 39-43.
    • (2001) 2001 Int. Conf. Electron. Packaging Proc. , pp. 39-43
    • Sasaki, K.1
  • 6
    • 10444221697 scopus 로고    scopus 로고
    • Process integration of 3D chip stack with vertical interconnection
    • Orlando, FL, June
    • K. Takahashi, et al., "Process Integration of 3D Chip Stack with Vertical Interconnection," Proc. 54th Electron. Components and Technol. Conf., Orlando, FL, June 2004, pp.601-609.
    • (2004) Proc. 54th Electron. Components and Technol. Conf. , pp. 601-609
    • Takahashi, K.1
  • 7
    • 23844447366 scopus 로고    scopus 로고
    • Wafer-level 3D interconnects via copper bonding
    • P. Morrow, et al., "Wafer-level 3D Interconnects via Copper Bonding" Conf. Proc. Adv. Metallization Conf. 2004, pp. 125-130, 2004.
    • (2004) Conf. Proc. Adv. Metallization Conf. 2004 , pp. 125-130
    • Morrow, P.1
  • 8
    • 0000983009 scopus 로고
    • Thermal response of metals to ultrashort-pulse laser excitation
    • Dec.
    • P. B. Corkum, F. Brunel, N. K. Sherman, and T. Srinivasan-Rao, "Thermal Response of Metals to Ultrashort-Pulse Laser Excitation," Phys. Rev. Lett., Vol. 61, No. 25, pp. 2886-2889, Dec. 1988.
    • (1988) Phys. Rev. Lett. , vol.61 , Issue.25 , pp. 2886-2889
    • Corkum, P.B.1    Brunel, F.2    Sherman, N.K.3    Srinivasan-Rao, T.4
  • 9
    • 36448999056 scopus 로고
    • Laser-cleaning techniques for removal of surface particles
    • Apr.
    • A. C. Tam, W. P. Leung, W. Zepka and W. Ziemlich, "Laser-cleaning techniques for removal of surface particles," J. Appl. Phys., Vol. 71, No. 7, pp. 3515-3523, Apr. 1992.
    • (1992) J. Appl. Phys. , vol.71 , Issue.7 , pp. 3515-3523
    • Tam, A.C.1    Leung, W.P.2    Zepka, W.3    Ziemlich, W.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.